| Age | Commit message (Collapse) | Author |
|
Details in comments.
PR kern/57240
XXX pullup-8
XXX pullup-9
XXX pullup-10
|
|
alpha_wmb() have been audited and fixed-up as necessary).
|
|
order reads with respect to writes. Remove now-redundant tc_wmb()
calls before tc_syncbus().
NFC on MIPS other than removing a redundant wbflush() (tc_wmb() followed
by tc_syncbus()).
|
|
|
|
|
|
Add missing "cc" and "memory" asm clobbers to the compiler can't
reorder memory access around these. The necessary memory barrier
instructions, mb, already appear in all the right places.
|
|
It is, and always has been, the caller's responsibility to ensure the
lock is initialized before it can be used -- otherwise the memory
could hold garbage; it is nonsensical to even attempt locking
operations on it before initialization.
So there's no need to issue explicit barriers here. The barrier
seems to have been introduced in sys/arch/alpha/alpha/lock_machdep.c
rev. 1.1 (since moved to inline asm in alpha/include/lock.h) and then
copied & pasted into several other architectures.
|
|
COPTS=-O0,
sprinkle `__always_inline' to make _mcount() be generated as a single function.
|
|
|
|
- sparc and sparc64 were not using version 0 sigcontext when there were
no arguments in the signal version. This was probably a bug.
- vax is using +1 the version numbers of the other archs.
- Only hppa was defining __LIBC12_SOURCE__ so it was getting a working
sigcontext before. all the other ports that supported sigcontext had
the compat code disabled.
[pointed out by thorpej, thanks!]
If we want to remove sigcontext support from userland at least now there
is less work to do so.
|
|
rather the macros.
|
|
atomic_cas_ulong().
- For arm, ia64, m68k, mips, or1k, riscv, vax: don't define our own
MUTEX_CAS(), as they either use atomic_cas_ulong() or equivalent
(atomic_cas_uint() on m68k).
- For alpha and sparc64, don't define MUTEX_CAS() in terms of their own
_lock_cas(), which has its own memory barriers; the call sites in
kern_mutex.c already have the appropriate memory barrier calls. Thus,
alpha and sparc64 can use default definition.
- For sh3, don't define MUTEX_CAS() in terms of its own _lock_cas();
atomic_cas_ulong() is strong-aliased to _lock_cas(), therefore defining
our own MUTEX_CAS() is redundant.
Per thread:
https://mail-index.netbsd.org/tech-kern/2021/07/25/msg027562.html
|
|
to get profiling data for each CPU.
In the current implementation, locks are acquired at the entrance of the mcount
internal function, so the higher the number of cores, the more lock conflict
occurs, making profiling performance in a MULTIPROCESSOR environment unusable
and slow. Profiling buffers has been changed to be reserved for each CPU,
improving profiling performance in MP by several to several dozen times.
- Eliminated cpu_simple_lock in mcount internal function, using per-CPU buffers.
- Add ci_gmon member to struct cpu_info of each MP arch.
- Add kern.profiling.percpu node in sysctl tree.
- Add new -c <cpuid> option to kgmon(8) to specify the cpuid, like openbsd.
For compatibility, if the -c option is not specified, the entire system can be
operated as before, and the -p option will get the total profiling data for
all CPUs.
|
|
- Use ufetch_32() instead of copyin() to fetch the instruction.
|
|
- Use __CTASSERT() instead of rolling our own compile-time assertion
using cpp.
- Use __BIT() &c instead of rolling our own.
- Improve some comments.
- Define a default FP_C and FPCR value that is self-consistent, and
initialize it properly at process creation time.
- Fix signal information when the trap shadow cannot be resolved.
- Use defined constants rather than magic numbers for the exception
summary bits.
- Add a machdep sysctl to enable FP software-completion debugging.
|
|
|
|
t_float.
|
|
as the default.
|
|
SGMAP DMA segments. If not specified, PAGE_SIZE will be used, as before.
|
|
valid bits in the PSL are the IPL and USER bits, the latter of which
will always be clear when in the kernel, and that all other bits MBZ.
So, when reading the PSL to get the current IPL, don't bother masking
with ALPHA_PSL_IPL_MASK.
|
|
some an odd IPL-related panic that seems to be related (that I can fairly
reliabily reproduce on an LCA45).
|
|
|
|
|
|
stacks are 16-byte aligned, an assumption made by the compiler
and recommended by the Alpha Architecture Handbook.
- cpu_lwp_fork(): Ensure 16-byte stack alignment if the caller specified
one.
Addresses root casue of PR port-alpha/54307 and PR toolchain/56153.
Many thanks to rin@ for performing the root cause analysis and testing
changes.
|
|
structures:
- alpha_shared_intr_alloc() no longer takes a "string length" argument,
and just uses kmem_asprintf() to create an "irq %u" string by default.
This is suitable for nearly every caller.
- Add a alpha_shared_intr_set_string() that allows callers to override
the default IRQ description string.
- Related: make alpha_shared_intr_string() return a const char *, since
no callers should need to modify the string directly now.
- Re-factor PCI shared interrupt structure allocation / initialization
into a new alpha_pci_intr_alloc(), which is suitable for nearly every
Alpha PCI platform. Callers are expected to first have initialized
the interrupt hardware to the quiescent state.
Adjust various call sites of above functions to account for changes,
even if they are not able to use the newly re-factored code.
|
|
|
|
the PCI interrupt initialization routine. Instead, register said routines
by systype in a link set, and look them up and invoke them in a new function
alpha_pci_intr_init().
|
|
reference count, and thus now many bits we need to scare up.
|
|
PT page reference count, but add an XXX comment stating the desire to
find a safely-unused field in the vm_page structure when pages are in-
use as PT pages, so that we can save the 8 bytes per page needed for
this.
|
|
referenced since some sources include <machine/param.h>.
|
|
|
|
pmap_tlb_context structure, and free them back in bulk after we
release all of our locks (as we do with PT pages that are freed).
|
|
|
|
the PV entry list pointer in struct vm_page_md. This reduces the size
of that structure from 16 bytes to 8, and will go a fair way to making
up for increasing the size of struct pv_entry in a future commit.
|
|
for a page.
|
|
UVM loan transaction, so use the vm_page::loan_count field as the PT
page reference count.
|
|
|
|
of vm_page structures. Define and use a generic routine to free such a list
back to UVM.
In pmap_remove_internal(), KASSERT that no PT pages are queued up to be
freed when removing mappings from the kernel pmap.
|
|
and into each CPU's pmap_percpu area. This pointer is constant for the
life of the pmap, and moving it gives us an additional 8 bytes in the
shared pmap structure.
Because the kernel pmap does not have per-CPU data, all places where we
need the kernel pmap's lev1map now just reference kernel_lev1map directly.
|
|
track it with a separate field in the pmap_percpu. Not only does this
reduce cache line contention ever so slightly, it also frees up a field
in the shared portion of the pmap structure.
|
|
No functional change.
|
|
that allows for up to 32GB of RAM to be direct-mapped if the PCI device
can issue a 64-bit address (the monster window lives at 0x10000000000).
Enable this window and provide this to the PCI bus as a "dmat64".
|
|
|
|
on alpha.
|
|
as the forward scenario, for example if a pmap_page_protect() to remove
all mappings results in the freeing of a PT page. It therefore needs
to do the same reference counting dance as pmap_tlb_shootdown_pv().
Also fix a use-after-free error in pmap_page_protect().
Add / tweak some assertions, and shrink the pmap::pm_count field from
long to unsigned int (which gave me a spare unsigned int field for
debugging purposes).
PR port-alpha/56201.
|
|
|
|
per-cpu information.
XXX mi_userret() also internally disables preemption. Should restructure
these to remove redundancies.
|
|
Rather than simply increment the interrupt depth for the clock interrupt,
we add 0x10. Why? Because while we only use a single Alpha IPL (4) for
IPL_{BIO,NET,TTY,VM}, technically the architecture specification suports
two in the OSF/1 PALcode (3 [low-pri] and 4 [high-pri]), meaning we could
conceiveably have intrdepth > 1 just for device interrupts.
Adding 0x10 here means that cpu_intr_p() can check for "intrdepth != 0" for
"in interrupt context" and CLKF_INTR() can check "(intrdepth & 0xf) != 0" for
"was processing interrupts when the clock interrupt happened".
|
|
http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/alpha/alpha/interrupt.c#rev1.93
by which interrupts *seem* to occupy 100% CPU time.
Now, we bump ci_intrdepth for clock interrupt. Therefore, if ci_intrdepth > 1
is observed in statclock(), CPU is actually occupied by interrupts.
Thanks jklos and thorpej for notice!
|
|
panic reported by John Klos on port-alpha:
- pmap_tlb_shootnow(): If we acquire a pmap's activation lock, we will
have raised the IPL on the current CPU to IPL_SCHED until we drop
the tlb_lock (due to how nested spin mutexes work). As such, when
we release the activation lock, forcibly lower our IPL back to IPL_VM
so that we can receive and process IPIs while waiting for other CPUs
to process the shootdowns.
- mutex_vector_enter(): Invoke SPINLOCK_SPIN_HOOK while spinning to acquire
a spin mutex. This is a nop on most platforms, but it's important on
the Alpha. Without this, IPIs (and thus TLB shootdowns) cannot be
processed if trying to acquire an IPL_SCHED spin mutex such as those
used by the scheduler.
...and while we're poking around in here:
- Rework the Alpha SPINLOCK_SPIN_HOOK to only check curcpu()->ci_ipis
if the current CPU's IPL is >= IPL_CLOCK (thus ensuring that preemption
is disabled and thus guaranteeing that curcpu() is stable). (Alpha does
not yet support kernel preemption, but this is now one less thing that
would need to be fixed.)
|