| Age | Commit message (Expand) | Author |
| 2022-03-03 | arm: Use device_set_private for cpuN. | riastradh |
| 2021-10-31 | Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep. | skrll |
| 2021-10-11 | For some classic CPUs, info->[id]cache_sets are not initialized. | rin |
| 2021-10-11 | pN steppings are used for ARM926EJ-S, although only r0 seems to be available. | rin |
| 2021-09-23 | Print the cache information in similar formats and arm and aarch64, e.g. | skrll |
| 2021-07-06 | Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This is | skrll |
| 2020-07-02 | Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradh | martin |
| 2020-06-29 | Implement fpu_kern_enter/leave for arm32. | riastradh |
| 2020-06-20 | KNF #includes | skrll |
| 2020-02-15 | Various updates and improvements to cpu start up on arm/aarch64 | skrll |
| 2020-01-22 | #ifdef whack-a-mole for the pmap_maxproc_set functionality | skrll |
| 2020-01-20 | s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pages | skrll |
| 2020-01-18 | Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) by | skrll |
| 2020-01-15 | port the arm64 cpu topology setup for big.little to arm. | mrg |
| 2020-01-09 | - Many small tweaks to the SMT awareness in the scheduler. It does a much | ad |
| 2020-01-09 | When attaching the first fdtbus, use the root "comptabile" (or failing that: | martin |
| 2020-01-08 | cpu_hatch is too late to report AP topology, do it at attach time instead | jmcneill |
| 2019-12-20 | Some more CPU topology stuff: | ad |
| 2019-12-02 | Take the basic CPU topology information we already collect, and use it | ad |
| 2019-10-20 | cpu_hatched_p only for MULTIPROCESSOR | jmcneill |
| 2019-10-19 | Increase aarch64 MAXCPUS to 256. | jmcneill |
| 2019-09-29 | aprint_debug_dev output alignment | skrll |
| 2019-09-08 | report A12 as A17 to the user. A12 is retcon'ed by ARM. | tnn |
| 2019-09-07 | Cortex A12 is marketed as A17 but has a distinct part number | tnn |
| 2019-03-17 | Wrap arm_cpu_marker if #ifdef MPDEBUG. | skrll |
| 2019-01-27 | Merge the [pgoyette-compat] branch | pgoyette |
| 2019-01-25 | Make sure ci_{smt,core,package}_id are all filled in appropriately. | skrll |
| 2019-01-03 | Read mpidr and cpuid from the secondary processor itself instead of the | jmcneill |
| 2019-01-03 | Start CPUs more like aarch64 by using a cpu_mpidr array (if populated) | skrll |
| 2019-01-02 | Don't overwrite the setting of cpu_core_id from mpidr | skrll |
| 2018-10-18 | Provide generic start code that assumes the MMU is off and caches are | skrll |
| 2018-10-08 | Trialing whitespace | skrll |
| 2018-10-06 | Use __BIT. NFC. | skrll |
| 2018-08-15 | KNF | skrll |
| 2018-08-15 | Fix includes (sys/cdefs.h then sys/param.h) | skrll |
| 2018-08-15 | Sprinkle #include "opt_cputypes.h" | skrll |
| 2018-08-10 | Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers of | maxv |
| 2017-09-16 | Add Cortex-A35 CPU ID. | matt |
| 2017-06-01 | remove checks for failure after memory allocation calls that cannot fail: | chs |
| 2016-07-11 | Add Cortex-A9 r1. | kiyohara |
| 2016-03-03 | Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs. | skrll |
| 2016-01-23 | Rename the cpu_id() define to cpu_idnum() so that it does not conflict with | christos |
| 2015-11-12 | change some register dumps from aprint_verbose to aprint_debug | jmcneill |
| 2015-07-08 | aprint_verbose [sa]ctlr | skrll |
| 2015-06-05 | Print the Revision ID regster (verbose) | skrll |
| 2015-05-17 | Print out mpidr on MP systems (verbose print) | matt |
| 2015-03-03 | cache type 12 is "write-back", from matt | jmcneill |
| 2014-11-27 | Add entry for Cortex-A17 r1 | matt |
| 2014-09-01 | Increase the `freqbuf' buffer that holds the result of humanize_number(). Now | reinoud |
| 2014-03-28 | Various MP changes. | matt |