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path: root/sys/arch/arm/arm32/cpu.c
AgeCommit message (Expand)Author
2022-03-03arm: Use device_set_private for cpuN.riastradh
2021-10-31Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.skrll
2021-10-11For some classic CPUs, info->[id]cache_sets are not initialized.rin
2021-10-11pN steppings are used for ARM926EJ-S, although only r0 seems to be available.rin
2021-09-23Print the cache information in similar formats and arm and aarch64, e.g.skrll
2021-07-06Assume all ARM11[37]6 r0 variants are missing ISAR and friends. This isskrll
2020-07-02Initialize ci_kfpu_spl earlier for secondary CPUs. From riastradhmartin
2020-06-29Implement fpu_kern_enter/leave for arm32.riastradh
2020-06-20KNF #includesskrll
2020-02-15Various updates and improvements to cpu start up on arm/aarch64skrll
2020-01-22#ifdef whack-a-mole for the pmap_maxproc_set functionalityskrll
2020-01-20s/_ARM_ARCH_6/ARM_MMU_EXTENDED/ in the #ifdef for the recent 4k pagesskrll
2020-01-18Use 4K pages on ARM_MMU_EXTENDED platforms (all armv[67] except RPI) byskrll
2020-01-15port the arm64 cpu topology setup for big.little to arm.mrg
2020-01-09- Many small tweaks to the SMT awareness in the scheduler. It does a muchad
2020-01-09When attaching the first fdtbus, use the root "comptabile" (or failing that:martin
2020-01-08cpu_hatch is too late to report AP topology, do it at attach time insteadjmcneill
2019-12-20Some more CPU topology stuff:ad
2019-12-02Take the basic CPU topology information we already collect, and use itad
2019-10-20cpu_hatched_p only for MULTIPROCESSORjmcneill
2019-10-19Increase aarch64 MAXCPUS to 256.jmcneill
2019-09-29aprint_debug_dev output alignmentskrll
2019-09-08report A12 as A17 to the user. A12 is retcon'ed by ARM.tnn
2019-09-07Cortex A12 is marketed as A17 but has a distinct part numbertnn
2019-03-17Wrap arm_cpu_marker if #ifdef MPDEBUG.skrll
2019-01-27Merge the [pgoyette-compat] branchpgoyette
2019-01-25Make sure ci_{smt,core,package}_id are all filled in appropriately.skrll
2019-01-03Read mpidr and cpuid from the secondary processor itself instead of thejmcneill
2019-01-03Start CPUs more like aarch64 by using a cpu_mpidr array (if populated)skrll
2019-01-02Don't overwrite the setting of cpu_core_id from mpidrskrll
2018-10-18Provide generic start code that assumes the MMU is off and caches areskrll
2018-10-08Trialing whitespaceskrll
2018-10-06Use __BIT. NFC.skrll
2018-08-15KNFskrll
2018-08-15Fix includes (sys/cdefs.h then sys/param.h)skrll
2018-08-15Sprinkle #include "opt_cputypes.h"skrll
2018-08-10Retire CPU_ARM2, CPU_ARM250 and CPU_ARM3, they are all leftovers ofmaxv
2017-09-16Add Cortex-A35 CPU ID.matt
2017-06-01remove checks for failure after memory allocation calls that cannot fail:chs
2016-07-11Add Cortex-A9 r1.kiyohara
2016-03-03Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.skrll
2016-01-23Rename the cpu_id() define to cpu_idnum() so that it does not conflict withchristos
2015-11-12change some register dumps from aprint_verbose to aprint_debugjmcneill
2015-07-08aprint_verbose [sa]ctlrskrll
2015-06-05Print the Revision ID regster (verbose)skrll
2015-05-17Print out mpidr on MP systems (verbose print)matt
2015-03-03cache type 12 is "write-back", from mattjmcneill
2014-11-27Add entry for Cortex-A17 r1matt
2014-09-01Increase the `freqbuf' buffer that holds the result of humanize_number(). Nowreinoud
2014-03-28Various MP changes.matt