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path: root/sys/arch/arm/cortex/gic.c
AgeCommit message (Expand)Author
2022-06-26build fix: remove includes of opt_gic.hjmcneill
2022-06-25Remove GIC_SPLFUNCS.jmcneill
2022-06-25pic: Update ci_cpl in pic_set_priority callback.jmcneill
2022-03-03arm: Use device_set_private for various drivers.riastradh
2022-01-02arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change.riastradh
2021-10-21Fix some conditionals to match gicv3 and add some comments to describeskrll
2021-09-26If an SGI or PPI is established after interrupts are enabled, make surejmcneill
2021-08-10Make gic_splfuncs optional and disable it by default until it has hadjmcneill
2021-08-10Use custom spl funcs for GIC and avoid unnecessary pmr register accessesjmcneill
2021-03-28Only target the boot cpu for real with SPI interrupts. I tried to doskrll
2021-02-23If we are committing a deferred splhigh() to hardware, no need to continue.jmcneill
2021-02-21Apply PMR optimizations from gicv3jmcneill
2021-02-09Avoid an extra daif read when dispatching interrupts by usingjakllsch
2020-12-03Provide and use a sev() macro for the sev instruction.skrll
2020-09-26G/C arm/atomic.hskrll
2020-07-27Remove CPU ID test in armgic_match. Perfectly normal to have GIC injmcneill
2020-07-12Avoid undefined behaviour. Detected by KUBSAN.skrll
2020-04-13Fix "left shift of 255 by 24 places cannot be represented in type 'int'"jmcneill
2018-11-16Use intr_establish_xnamejmcneill
2018-09-10armgic_ipi_send: use GIC interface number, not CPU index, when settingjmcneill
2018-09-10Update sc_mptargets atomically, as PEs will be started up in parallel w/o loc...jmcneill
2018-07-15Support pic_set_affinity and pic_get_affinityjmcneill
2018-04-28Cover all pic_maxsources lines for armgic_cpu_init_priorities() andjakllsch
2018-04-01Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)ryo
2018-02-07PR# port-evbarm/49468: Cortex GIC assertion triggered on Allwinner A80 SoCjmcneill
2017-07-14KNFskrll
2017-06-29ARM Trusted Firmware reserves SGIs 8-15 for secure use. Even without ATF,jmcneill
2017-06-28Revert the KERNHIST for now it causes problemsskrll
2017-06-22If we see GICC_IAR_IRQ_SSPURIOUS we should also stop looking for irqsskrll
2017-06-22Wrap long lineskrll
2017-06-22Print the GICC_IIDR when AB_DEBUGskrll
2017-06-22Add 'armgichist' KERNHIST for (future) debugging.skrll
2017-06-18Don't assume that CPU index = GIC CPU interface number. We can determinejmcneill
2017-06-05Clean out some #if 0'ed or //'ed codeskrll
2017-06-04Initialise all the SGI/PPI priorities for all CPUs to mask the interruptsskrll
2017-05-30Use an FDT-based ARM_INTR_IMPL for Tegra.jmcneill
2015-07-29Adjust some of IPLs of various IPIs.matt
2015-04-15Add separate IPI routines for IPI_AST and IPI_KPREEMPT.matt
2015-04-11Add a pic_cpus to the softc which specifies which cpus the pic can sendmatt
2015-04-09All SGIs are MPSAFE so establish them as such.matt
2015-03-20Trailing whitespaceskrll
2015-03-12G/C armgic_last_priorityskrll
2015-03-03in armgic_establish_irq, make sure to write the new value to GICD_ICFGRn when...jmcneill
2015-03-02sc_gic_lines is the total number of valid lines but pic_sources[] is sparse; ...jmcneill
2014-10-29Only target boot cpu for SPIs atm. Fix a couple of bugs in the nowskrll
2014-10-29Sprinkle #include "opt_multiprocessor.h"skrll
2014-05-19Implement MI IPI interface with cross-call support.rmind
2014-04-27When dealing with the PMR register, only use non-secure priority values.matt
2014-04-13Move aprint to print sooner.matt
2014-03-28Various MP changes.matt