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path: root/sys/arch/arm/cortex/gic_reg.h
AgeCommit message (Expand)Author
2020-11-22Add GICD_CTRL_EnableGrp1S definition.jmcneill
2019-05-02Fix definition of GICD_IROUTER; the input to this macro is the INTID,jmcneill
2018-11-24Handle ThunderX errataskrll
2018-11-13Update GICD_CTLR reg bit definitions to reflect the layout of the registerjmcneill
2018-11-09Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and thejmcneill
2018-08-08Update for GICv3jmcneill
2017-06-22Naming consistency for (as yet) unused registerskrll
2015-06-09Correct a commentskrll
2015-06-05Add an define for spurious interrupt number 1022skrll
2014-04-27When dealing with the PMR register, only use non-secure priority values.matt
2014-03-28Various MP changes.matt
2012-09-01Add Cortex-A9 support including the ARM Generic Interrupt Controllermatt