| Age | Commit message (Expand) | Author |
|---|---|---|
| 2020-11-22 | Add GICD_CTRL_EnableGrp1S definition. | jmcneill |
| 2019-05-02 | Fix definition of GICD_IROUTER; the input to this macro is the INTID, | jmcneill |
| 2018-11-24 | Handle ThunderX errata | skrll |
| 2018-11-13 | Update GICD_CTLR reg bit definitions to reflect the layout of the register | jmcneill |
| 2018-11-09 | Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and the | jmcneill |
| 2018-08-08 | Update for GICv3 | jmcneill |
| 2017-06-22 | Naming consistency for (as yet) unused register | skrll |
| 2015-06-09 | Correct a comment | skrll |
| 2015-06-05 | Add an define for spurious interrupt number 1022 | skrll |
| 2014-04-27 | When dealing with the PMR register, only use non-secure priority values. | matt |
| 2014-03-28 | Various MP changes. | matt |
| 2012-09-01 | Add Cortex-A9 support including the ARM Generic Interrupt Controller | matt |
