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path: root/sys/arch/arm/cortex/gicv3.c
AgeCommit message (Expand)Author
2022-06-26build fix: remove includes of opt_gic.hjmcneill
2022-06-25gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappingsjmcneill
2022-06-25Remove GIC_SPLFUNCS.jmcneill
2022-06-25pic: Update ci_cpl in pic_set_priority callback.jmcneill
2022-03-28arm/cortex: Use container_of, not bespoke offsetof arithmetic.riastradh
2021-10-02Trailing whitespaceskrll
2021-09-26If an SGI or PPI is established after interrupts are enabled, make surejmcneill
2021-09-11GIC: Support SPI affinity routing before secondary CPUs have hatched.jmcneill
2021-08-10Make gic_splfuncs optional and disable it by default until it has hadjmcneill
2021-08-10Use custom spl funcs for GIC and avoid unnecessary pmr register accessesjmcneill
2021-03-28Disable 1ofN distribution of SPIs by default. This is a workaround for anjmcneill
2021-02-23If we are committing a deferred splhigh() to hardware, no need to continue.jmcneill
2021-02-21Keep current hardware priority value in struct cpu_info and use it insteadjmcneill
2021-02-09fix build without MULTIPROCESSORryo
2021-02-07Optimize hardware priority updates.jmcneill
2021-01-16Remove MAXCPUS dependency.jmcneill
2020-12-22When lpiconf flushing is required, make sure to flush to PoC and not PoU.jmcneill
2020-12-11Fix spelling in comment.jmcneill
2020-12-04gicv3: Only use 1 of N SPI distribution when the feature is available.jmcneill
2020-11-24Improve detection of NS vs S views of priorities.jmcneill
2020-11-22Fix interrupt priorities on N1 SDP.jmcneill
2020-11-21Add a per-CPU event counter that counts every time an interrupt handler isjmcneill
2020-11-01sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_andjmcneill
2020-11-01Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have workedjmcneill
2020-11-01Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering withjmcneill
2020-11-01gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb()jmcneill
2020-11-01gicv3_irq_handler: No need to call gicv3_set_priority if we are already atjmcneill
2020-11-01gicv3_ipi_send: simplify logic in kcp != NULL case given that we know thatjmcneill
2020-10-30Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.skrll
2020-04-13Apply similar fix from gic.c that fixed "left shift of 255 by 24 placesjmcneill
2020-02-13Make intr affinity work with MSIs againjmcneill
2020-02-13Since all ITS instances share a common LPI configuration table, used ajmcneill
2019-12-24Traiing whitespaceskrll
2019-09-05- Use pic_do_pending_ints in intr handlerjmcneill
2019-06-30Fix size of LPI pending table allocation and enable caching of LPI confjmcneill
2019-06-26Change how we detect secure vs non-secure access.jmcneill
2019-06-17Improve priority handling for cases where access is secure, from OpenBSD.jmcneill
2019-06-12revert rev 1.4:mrg
2019-06-12Revert "Route all interrupts to the primary PE by default"jmcneill
2019-06-12Route all interrupts to the primary PE by defaultjmcneill
2019-06-12Adjust priority mappings, NFCIjmcneill
2018-11-23Fix LPI pending table size, use correct LPI conf offset in gicv3_lpi_block_ir...jmcneill
2018-11-21kcpuset_ffs returns the cpu number plus one, so make sure to subtract itjmcneill
2018-11-17Use intr_establish_xnamejmcneill
2018-11-15Instead of disabling preemption, set the binary point field to the minimum su...jmcneill
2018-11-13Update GICD_CTLR reg bit definitions to reflect the layout of the registerjmcneill
2018-11-13Save a few pages by only allocating LPI pending tables for "ncpu" instead of ...jmcneill
2018-11-10Implement pic_get_affinity/pic_set_affinity for LPIs via ITSjmcneill
2018-11-10Implement pic_get_affinity/pic_set_affinity for SPIsjmcneill
2018-11-09Add support for GICv3 Locality-specific Periphal Interrupts (LPIs) and thejmcneill