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path: root/sys/arch/arm/cortex/pl310.c
AgeCommit message (Expand)Author
2021-10-02Trailing whitespaceskrll
2019-01-19Remove hard requirement for "offset" property on Cortex-A5. This is not requi...jmcneill
2018-06-20Add l2cc support.hkenken
2015-02-27allow arml2cc to be used on Cortex-A5 if the "offset" property is specifiedjmcneill
2014-12-01clean the a9 l2 cache before turning it on.matt
2014-04-16Allow l2cc base to gotten from device properties.matt
2014-03-20pl310 cache is PIPTmatt
2014-02-23#include <arm/locore.h>matt
2013-06-17KASSERT -> KASSERTMSGmatt
2013-02-13simplify cache range opmatt
2013-01-22Don't "sync" atomic ops.matt
2012-11-28Make these compile with gcc4.1 and binutils 2.16matt
2012-11-01Invalidate the L2 cache before enabling it.matt
2012-10-17Add a missing mutex exit.matt
2012-09-22Don't use an asm in pmap_activate to update the TTBR, use cpu_setttb insteadmatt
2012-09-14Add L2 cache flush routines. (not yet enabled).matt
2012-09-07Don't disable the L2C is it isn't enabled.matt
2012-09-07Switch cortex_a9 back to need_ptesync = 1matt
2012-09-02Add "write-back" before Unifiedmatt
2012-09-02Add driver to attach ARM PL210 L2 Cache Controllermatt