summaryrefslogtreecommitdiff
path: root/sys/arch/arm/cortex
AgeCommit message (Expand)Author
2021-11-13fix aarch64 buildjakllsch
2021-11-12gtmr: Add support for arm,cpu-registers-not-fw-configured property.jmcneill
2021-10-31Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail toskrll
2021-10-31Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.skrll
2021-10-31Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.jmcneill
2021-10-30Add __HAVE_PREEMPTION support to gic_splfuncs asm funcs.jmcneill
2021-10-30Implement gic_splraise and the gic_splx fast path in asm (armv8).jmcneill
2021-10-21Fix some conditionals to match gicv3 and add some comments to describeskrll
2021-10-02Trailing whitespaceskrll
2021-09-26Add missing insn barrierjmcneill
2021-09-26If an SGI or PPI is established after interrupts are enabled, make surejmcneill
2021-09-20Make _splraise/_spllower/splx functions available to modules again.jmcneill
2021-09-18gic_splx: performance optimizationsjmcneill
2021-09-11GIC: Support SPI affinity routing before secondary CPUs have hatched.jmcneill
2021-09-09If we get a spurious interrupt, log a debug message and ignore it.jmcneill
2021-08-30- Add an isb before cnt[pv]_ctl readjmcneill
2021-08-10Make gic_splfuncs optional and disable it by default until it has hadjmcneill
2021-08-10Use custom spl funcs for GIC and avoid unnecessary pmr register accessesjmcneill
2021-08-07Merge thorpej-cfargs2.thorpej
2021-04-24Merge thorpej-cfargs branch:thorpej
2021-03-28Disable 1ofN distribution of SPIs by default. This is a workaround for anjmcneill
2021-03-28Only target the boot cpu for real with SPI interrupts. I tried to doskrll
2021-03-14Remove an unnecessary if statement in gic_v2m_msi_alloc when finding askrll
2021-02-23If we are committing a deferred splhigh() to hardware, no need to continue.jmcneill
2021-02-21Apply PMR optimizations from gicv3jmcneill
2021-02-21Keep current hardware priority value in struct cpu_info and use it insteadjmcneill
2021-02-09fix build without MULTIPROCESSORryo
2021-02-09Avoid an extra daif read when dispatching interrupts by usingjakllsch
2021-02-07Optimize hardware priority updates.jmcneill
2021-01-18Fix a commentjmcneill
2021-01-16Remove MAXCPUS dependency.jmcneill
2020-12-24trailing whitespacejmcneill
2020-12-22When lpiconf flushing is required, make sure to flush to PoC and not PoU.jmcneill
2020-12-11Simplify gits_command by getting rid of the _BYTE_ORDER test and justjmcneill
2020-12-11Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-Xjmcneill
2020-12-11Fix spelling in comment.jmcneill
2020-12-04gicv3: Only use 1 of N SPI distribution when the feature is available.jmcneill
2020-12-03Provide and use a sev() macro for the sev instruction.skrll
2020-12-02comparision -> comparisonwiz
2020-11-28Fix buildskrll
2020-11-24Improve detection of NS vs S views of priorities.jmcneill
2020-11-22Fix interrupt priorities on N1 SDP.jmcneill
2020-11-22Add GICD_CTRL_EnableGrp1S definition.jmcneill
2020-11-21Add a per-CPU event counter that counts every time an interrupt handler isjmcneill
2020-11-01sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_andjmcneill
2020-11-01Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have workedjmcneill
2020-11-01Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering withjmcneill
2020-11-01gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb()jmcneill
2020-11-01gicv3_irq_handler: No need to call gicv3_set_priority if we are already atjmcneill
2020-11-01gicv3_ipi_send: simplify logic in kcp != NULL case given that we know thatjmcneill