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path: root/sys/arch/arm/cortex
AgeCommit message (Expand)Author
2020-11-22Fix interrupt priorities on N1 SDP.jmcneill
2020-11-22Add GICD_CTRL_EnableGrp1S definition.jmcneill
2020-11-21Add a per-CPU event counter that counts every time an interrupt handler isjmcneill
2020-11-01sc_enabled_sgippi can be updated from any CPU, so use atomic_or/atomic_andjmcneill
2020-11-01Remove unused __HAVE_PIC_FAST_SOFTINTS block. It never would have workedjmcneill
2020-11-01Add an isb() barrier after ICC_SGI1R_EL1 write to prevent reordering withjmcneill
2020-11-01gicv3_set_priority: ICC_PMR_EL1 is self-synchronizing so no need for isb()jmcneill
2020-11-01gicv3_irq_handler: No need to call gicv3_set_priority if we are already atjmcneill
2020-11-01gicv3_ipi_send: simplify logic in kcp != NULL case given that we know thatjmcneill
2020-10-30Retire arm_[di]sb in favour of the isb() and dsb(sy) macro invocations.skrll
2020-09-29Collapse all CPU_CORTEXA<n> options into CPU_CORTEX and do runtimejmcneill
2020-09-26G/C arm/atomic.hskrll
2020-09-24need to swap on big endian machines.ryo
2020-07-27Remove CPU ID test in armgic_match. Perfectly normal to have GIC injmcneill
2020-07-12Avoid undefined behaviour. Detected by KUBSAN.skrll
2020-05-07Do not store a pointer to the passed in struct pci_attach_argsjmcneill
2020-04-13Apply similar fix from gic.c that fixed "left shift of 255 by 24 placesjmcneill
2020-04-13Fix "left shift of 255 by 24 places cannot be represented in type 'int'"jmcneill
2020-03-05Revert "Include opt_diagnostic.h for DIAGNOSTIC."riastradh
2020-03-05Include opt_diagnostic.h for DIAGNOSTIC.riastradh
2020-02-13Make intr affinity work with MSIs againjmcneill
2020-02-13Since all ITS instances share a common LPI configuration table, used ajmcneill
2020-02-01Use kmem_zalloc for its state, fixes possible crash if a driver tries tojmcneill
2020-01-17Set msi_id to its_idjmcneill
2019-12-24Traiing whitespaceskrll
2019-12-02 Use PCI_MSIX_"TBL"BIR_MASK instead of PCI_MSIX_"PBA"BIR_MASK for MSI-X table.msaitoh
2019-10-14Add support for Amazon's Graviton MSI controller.jmcneill
2019-09-05- Use pic_do_pending_ints in intr handlerjmcneill
2019-08-14Various fixes / changesskrll
2019-08-12Add support for physical timers and sprinkle isb where needed.jmcneill
2019-08-10Add a driver for the A5/A9 Private timer.skrll
2019-08-10spaces to tabskrll
2019-07-30Fix loop to calculate prescaler divisor.skrll
2019-07-27Rename a register define to make it more obvious it's watchdog onlyskrll
2019-06-30Cleanup ThunderX quirk and print cache / shareability details for ITT tablesjmcneill
2019-06-30Fix size of LPI pending table allocation and enable caching of LPI confjmcneill
2019-06-30Enable caching of ITS tables when possiblejmcneill
2019-06-29Restore original size calculation for MAPD and don't disable MSI/MSIX on devi...jmcneill
2019-06-29Rename lpi pic to gicv3-its when an ITS is foundjmcneill
2019-06-26Remove unused fieldjmcneill
2019-06-26Change how we detect secure vs non-secure access.jmcneill
2019-06-23Pass correct EventID to MOVI and INV commandsjmcneill
2019-06-23Remove unused variable (build fix)jmcneill
2019-06-23Ensure that the "size" parameter of MAPD matches the size of the ITT beingjmcneill
2019-06-17Improve priority handling for cases where access is secure, from OpenBSD.jmcneill
2019-06-17- Disable MSI/MSI-X when making changesjmcneill
2019-06-16Pass correct event ID with MOVI commandsjmcneill
2019-06-16- Disable MSI/MSI-X when making changesjmcneill
2019-06-16Disable counter before updating cval/tvaljmcneill
2019-06-12Allow set_affinity calls before PEs are brought online. We store thejmcneill