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path: root/sys/arch/arm/include/armreg.h
AgeCommit message (Expand)Author
2022-12-03move ARMv7 PMC register definitions to armreg.h from tprof_armv7.cryo
2022-05-20s/auxillary/auxiliary/ in comments.andvar
2021-11-27Add the Cortex A17 Diagnostic control registersskrll
2021-11-13Set ACTLR.SMP=1 on Cortex-A17jmcneill
2021-10-10Add a placeholder for PRRRskrll
2021-09-03fix typos in comments, mainly s/extention/extension/ and s/sufficent/sufficient/andvar
2021-01-31Fix (unused) PRRR_NOSn #defineskrll
2019-10-29Explicitly annotate FPU requirements for LLVM MC.joerg
2019-08-12Add support for physical timers and sprinkle isb where needed.jmcneill
2019-05-02It's the Normal Memory Remap Register (not Normal Region Remap Register)skrll
2019-05-02Fix Normal Region Remap Register bitmask namesskrll
2019-01-30add gtmr_cntv_cval_writejmcneill
2018-08-15Some CPU specific ACTLR bit definitionsskrll
2018-08-12Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrapskrll
2018-07-15Add some PMC event registersjmcneill
2018-05-14Workaround A-008585 errata in GTMR.joerg
2018-04-01Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)ryo
2018-03-20separate cputypes.h for CPU_ID_* from armreg.h,ryo
2018-03-02insert a couple of .fpu directives when we access the vfp registers whilechristos
2018-01-24Remove port-acorn26skrll
2017-12-20One copy of the generic timer register defines is enough for anyone. Theskrll
2017-12-20Correct ARM_CNTKCTL_PL0[VP]CTEN values. NFC as nothing uses them.skrll
2017-12-17Typo in commentskrll
2017-10-24Some more registersskrll
2017-09-16Add Cortex-A35 CPU ID.matt
2016-05-17Fix CORTEXA9Rx definitions.msaitoh
2016-03-03Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.skrll
2015-10-15No need to shoutskrll
2015-10-15Setting actlr.bit15=1 (Force in order issue in the branch execution unit)skrll
2015-06-09Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7skrll
2015-05-30Add Revision ID registerskrll
2015-05-20move register accessor macros for MPIDR and AUXFMC0 to armreg.hhsuenaga
2015-04-27Trailing whitespaceskrll
2015-04-27ARM spells the System Control Register SCTLRskrll
2014-11-27Add Cortex-A17 IDmatt
2014-10-15Fix dccmvau. Add bpimva.skrll
2014-10-15Fix bpiall and the comment against bpiallisskrll
2014-10-12Minor amendment/corrections.skrll
2014-09-16Remove redundant CORTEXA9_AUXCTL definesmatt
2014-04-14Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.matt
2014-04-13Add tpidruro and tpidrurw inlinesmatt
2014-03-29Add scr inlinematt
2014-03-26Add NSACRmatt
2014-03-07Restrict arm_cond_ok_p to when !__ASSEMBLER && _KERNEL is true.matt
2014-03-07Avoid a gcc4.8 bogon.matt
2014-03-05Define all the instruction conditions.matt
2014-03-03More control bits.matt
2014-03-01Fix typosmatt
2014-03-01defines/inlines for cortex a5/a7 tlbdata opsmatt
2014-02-26Add more MMU registersmatt