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armreg.h
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Author
2022-12-03
move ARMv7 PMC register definitions to armreg.h from tprof_armv7.c
ryo
2022-05-20
s/auxillary/auxiliary/ in comments.
andvar
2021-11-27
Add the Cortex A17 Diagnostic control registers
skrll
2021-11-13
Set ACTLR.SMP=1 on Cortex-A17
jmcneill
2021-10-10
Add a placeholder for PRRR
skrll
2021-09-03
fix typos in comments, mainly s/extention/extension/ and s/sufficent/sufficient/
andvar
2021-01-31
Fix (unused) PRRR_NOSn #define
skrll
2019-10-29
Explicitly annotate FPU requirements for LLVM MC.
joerg
2019-08-12
Add support for physical timers and sprinkle isb where needed.
jmcneill
2019-05-02
It's the Normal Memory Remap Register (not Normal Region Remap Register)
skrll
2019-05-02
Fix Normal Region Remap Register bitmask names
skrll
2019-01-30
add gtmr_cntv_cval_write
jmcneill
2018-08-15
Some CPU specific ACTLR bit definitions
skrll
2018-08-12
Provide and use cpu_mpidr_aff_read in psci_fdt_bootstrap
skrll
2018-07-15
Add some PMC event registers
jmcneill
2018-05-14
Workaround A-008585 errata in GTMR.
joerg
2018-04-01
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
ryo
2018-03-20
separate cputypes.h for CPU_ID_* from armreg.h,
ryo
2018-03-02
insert a couple of .fpu directives when we access the vfp registers while
christos
2018-01-24
Remove port-acorn26
skrll
2017-12-20
One copy of the generic timer register defines is enough for anyone. The
skrll
2017-12-20
Correct ARM_CNTKCTL_PL0[VP]CTEN values. NFC as nothing uses them.
skrll
2017-12-17
Typo in comment
skrll
2017-10-24
Some more registers
skrll
2017-09-16
Add Cortex-A35 CPU ID.
matt
2016-05-17
Fix CORTEXA9Rx definitions.
msaitoh
2016-03-03
Get the RPI3 working (in aarch32 mode) by recognising Cortex A53 CPUs.
skrll
2015-10-15
No need to shout
skrll
2015-10-15
Setting actlr.bit15=1 (Force in order issue in the branch execution unit)
skrll
2015-06-09
Use TTBR_[UM]PATTR in a9_mpsubr.S as well as cpufunc_asm_armv7
skrll
2015-05-30
Add Revision ID register
skrll
2015-05-20
move register accessor macros for MPIDR and AUXFMC0 to armreg.h
hsuenaga
2015-04-27
Trailing whitespace
skrll
2015-04-27
ARM spells the System Control Register SCTLR
skrll
2014-11-27
Add Cortex-A17 ID
matt
2014-10-15
Fix dccmvau. Add bpimva.
skrll
2014-10-15
Fix bpiall and the comment against bpiallis
skrll
2014-10-12
Minor amendment/corrections.
skrll
2014-09-16
Remove redundant CORTEXA9_AUXCTL defines
matt
2014-04-14
Support (untested) SHEEVA_L2_CACHE and SHEEVA_L2_CACHE_WT options.
matt
2014-04-13
Add tpidruro and tpidrurw inlines
matt
2014-03-29
Add scr inline
matt
2014-03-26
Add NSACR
matt
2014-03-07
Restrict arm_cond_ok_p to when !__ASSEMBLER && _KERNEL is true.
matt
2014-03-07
Avoid a gcc4.8 bogon.
matt
2014-03-05
Define all the instruction conditions.
matt
2014-03-03
More control bits.
matt
2014-03-01
Fix typos
matt
2014-03-01
defines/inlines for cortex a5/a7 tlbdata ops
matt
2014-02-26
Add more MMU registers
matt
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