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path: root/sys/arch/mips/cavium/dev
AgeCommit message (Expand)Author
2023-03-21octrnm(4): Raise delay on startup.riastradh
2022-09-29Remove unnecessary include of <sys/malloc.h>.skrll
2022-09-29Trailing whitespaceskrll
2022-09-18Eliminate use of IFF_OACTIVE.thorpej
2022-06-03fix folloing->following typos in more files.andvar
2022-05-23s/controll/control/ in comments.andvar
2022-05-04s/entires/entries/andvar
2022-04-17fix various typos in comments.andvar
2022-03-19rnd(9): Omit needless locks in various HWRNG drivers.riastradh
2022-03-19rnd(9): Adjust IPL of locks used by rndsource callbacks.riastradh
2022-01-26Fix initialization of the register map by using the com_init_regs()martin
2021-12-28sys: Use preempt_point and preempt_needed, not open-coded versions.riastradh
2021-12-05s/multple/multiple/ in comment.msaitoh
2021-11-10s/endianess/endianness/msaitoh
2021-09-17some love to double letters (in comments).andvar
2021-08-07Merge thorpej-cfargs2.thorpej
2021-05-27Move the send queue checking to a new function, and also call thissimonb
2021-05-27Schedule the send cleanup function for next tick in cnmac_start(). Insimonb
2021-05-14Fix a missed bitmask to __SHIFTOUT conversion in rev 1.12.simonb
2021-05-05Sprinkle some static.simonb
2021-04-24Merge thorpej-cfargs branch:thorpej
2021-03-24Remove somewhat dubious empty octfpa_desc structure.simonb
2021-01-27Rename of_match_compat_data() to of_compatible_match(). Similarly,thorpej
2021-01-27Use DEVICE_COMPAT_EOL.thorpej
2021-01-25Since we're using designated initialisers for compat data, we shouldthorpej
2021-01-18Remove "struct of_compat_data" and replace its usage withthorpej
2021-01-15Add 'const char *xname' arg to fdtbus_interrupt_controller_func .establishjmcneill
2021-01-04malloc(9) -> kmem(9)thorpej
2020-10-15Initialise xhci_softc sc_iosjmcneill
2020-08-04Add some CvmCtl bits from newer cnMIPS cores.simonb
2020-07-26Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, movesimonb
2020-07-20Fix coreX/IP4 summary register offsetsjmcneill
2020-07-17Remove 2 CPU limit in OCTEON interrupt controller driver.jmcneill
2020-07-17Don't use a reserved value for the USB endian CSR selects andsimonb
2020-07-16Add USB3 support.jmcneill
2020-07-16Add driver for Cavium Interrupt Bus.jmcneill
2020-07-16FDT support for Cavium OCTEON MIPS SoCs. WIP.jmcneill
2020-06-27Add new file containing a couple of UART prototypes.simonb
2020-06-23Add support for a very simple output-only console so early printf() can work.simonb
2020-06-23Make sure we only attach to CN3xxx/CN5xxx.simonb
2020-06-23Redo cnmac attachments - cnmacM @ gmxN @ pip0 @ iobussimonb
2020-06-23Redo cnmac attachments - cnmacM @ gmxN @ pip0 @ iobussimonb
2020-06-23Cleanup - mostly removing unused code and defines.simonb
2020-06-23Minor tweaks and cleanup.simonb
2020-06-23Remove unused include files.simonb
2020-06-23Remove USB controller register definitions, these match dwc2 core andsimonb
2020-06-23Remove unused octeon*usb*var*h includes.simonb
2020-06-22Remove more snprintb _BITS bits.simonb
2020-06-22Remove unused snprintb format strings.simonb
2020-06-22Remove unmaintained CNMAC_DEBUG debug code.simonb