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cpuregs.h
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Author
2021-11-16
Use the architecture documented name ULR for the RDHWR user local
simonb
2021-11-16
Add some comments for the RDHWR register numbers.
simonb
2021-11-16
Only need one #define for MIPS_HWR_CPUNUM.
simonb
2021-11-01
fix typos, mainly in words minimum and maximum, but also few others.
andvar
2021-08-09
s/definitons/definitions/
andvar
2021-05-29
Update the FPU register names and bit definitions to something somewhat
simonb
2021-03-17
Handle gas/gcc generating a break/trap 6 for integer overflow and
simonb
2020-08-22
Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64
simonb
2020-08-02
Add a few more perfcnt CP0 registers.
simonb
2020-07-31
Add two cnMIPS III COP0 register names.
simonb
2020-07-29
Add definitions for the CP0 WatchLo/WatchHi registers.
simonb
2020-07-26
#define<tab>
simonb
2020-07-26
Add CP0 Config Registers 6 and 7.
simonb
2020-07-26
Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, move
simonb
2020-07-20
Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.
simonb
2020-07-20
Add an extra bitfield in MIPS_COP_0_EBASE.
simonb
2020-07-13
Remove a magic number.
simonb
2020-05-24
Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU number
simonb
2020-05-23
Add CX73xx and CXF75xx Cavium Octeon PRIDs.
simonb
2020-05-07
Add PRID definition for newer SiByte SB1 cores (rev 0x11).
simonb
2017-05-07
Trailing whitespace
skrll
2016-07-11
Change MIPS to use the common pmap code.
matt
2015-06-11
Add a few MIPS32 R3 bits
matt
2015-06-10
Add MIPS 1074K
matt
2015-06-07
Define COP0 register that use select value in <mips/cpuregs.h>
matt
2015-06-01
Rework cavium support in preparation for MULTIPROCESSOR support
matt
2015-04-29
Initial import of Cavium Octeon and Octeon Plus SoC and
hikaru
2014-11-22
deal with Ingenic XBurst CPUs
macallan
2011-10-29
Add Broadcom BCM3302 CPU to the table.
jakllsch
2011-09-22
support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory and
macallan
2011-08-27
loongson2f support:
bouyer
2011-08-02
Add Loongson2 DIAG register definitions (partial)
matt
2011-07-31
Add define for loongson2 DIAG register
matt
2011-04-06
Fix some comments.
matt
2011-03-15
Add separate support for MIPS32R2 and MIPS64R2.
matt
2011-03-03
Change MIPS_CP0FL_CONFIG*
matt
2011-02-20
Major merge forward from matt-nb5-mips64.
matt
2011-01-26
Add support for the Extensible MIPS ("eMIPS") platform. The
pooka
2010-02-27
Spell "exception" properly.
snj
2009-12-14
Merge from matt-nb5-mips64
matt
2009-08-06
LOONGSON2 is a MIPS III
matt
2009-08-01
Add Loongson2 chip ids
matt
2008-02-19
Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.
simonb
2007-10-17
Merge the ppcoea-renovation branch to HEAD.
garbled
2007-10-16
Recognise the R2000A cpu as found in some pmaxen.
simonb
2006-08-26
Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_t
matt
2006-05-15
Fix typo in MIPS3_SR_EIE.
simonb
2005-12-20
Add basic support for Alchemy Au1550 processor (CPU and devices).
tron
2005-12-11
merge ktrace-lwp.
christos
2005-11-05
Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()
tsutsui
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