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path: root/sys/arch/mips/include/cpuregs.h
AgeCommit message (Expand)Author
2021-11-16Use the architecture documented name ULR for the RDHWR user localsimonb
2021-11-16Add some comments for the RDHWR register numbers.simonb
2021-11-16Only need one #define for MIPS_HWR_CPUNUM.simonb
2021-11-01fix typos, mainly in words minimum and maximum, but also few others.andvar
2021-08-09s/definitons/definitions/andvar
2021-05-29Update the FPU register names and bit definitions to something somewhatsimonb
2021-03-17Handle gas/gcc generating a break/trap 6 for integer overflow andsimonb
2020-08-22Remove bogus duplicate MIPS_COP_0_CONTEXT definition, it's not a MIPS32/64simonb
2020-08-02Add a few more perfcnt CP0 registers.simonb
2020-07-31Add two cnMIPS III COP0 register names.simonb
2020-07-29Add definitions for the CP0 WatchLo/WatchHi registers.simonb
2020-07-26#define<tab>simonb
2020-07-26Add CP0 Config Registers 6 and 7.simonb
2020-07-26Remove mostly duplicate MIPS spec CP0 regs from octeon_corereg.h, movesimonb
2020-07-20Expose the width of the MIPS_EBASE_CPUNUM bitfield for asm code.simonb
2020-07-20Add an extra bitfield in MIPS_COP_0_EBASE.simonb
2020-07-13Remove a magic number.simonb
2020-05-24Add mipsNN_cp0_rdhwr_cpunum() which returns the current CPU numbersimonb
2020-05-23Add CX73xx and CXF75xx Cavium Octeon PRIDs.simonb
2020-05-07Add PRID definition for newer SiByte SB1 cores (rev 0x11).simonb
2017-05-07Trailing whitespaceskrll
2016-07-11Change MIPS to use the common pmap code.matt
2015-06-11Add a few MIPS32 R3 bitsmatt
2015-06-10Add MIPS 1074Kmatt
2015-06-07Define COP0 register that use select value in <mips/cpuregs.h>matt
2015-06-01Rework cavium support in preparation for MULTIPROCESSOR supportmatt
2015-04-29Initial import of Cavium Octeon and Octeon Plus SoC andhikaru
2014-11-22deal with Ingenic XBurst CPUsmacallan
2011-10-29Add Broadcom BCM3302 CPU to the table.jakllsch
2011-09-22support BUS_SPACE_MAP_PREFETCH in order to allow mapping device memory andmacallan
2011-08-27loongson2f support:bouyer
2011-08-02Add Loongson2 DIAG register definitions (partial)matt
2011-07-31Add define for loongson2 DIAG registermatt
2011-04-06Fix some comments.matt
2011-03-15Add separate support for MIPS32R2 and MIPS64R2.matt
2011-03-03Change MIPS_CP0FL_CONFIG*matt
2011-02-20Major merge forward from matt-nb5-mips64.matt
2011-01-26Add support for the Extensible MIPS ("eMIPS") platform. Thepooka
2010-02-27Spell "exception" properly.snj
2009-12-14Merge from matt-nb5-mips64matt
2009-08-06LOONGSON2 is a MIPS IIImatt
2009-08-01Add Loongson2 chip idsmatt
2008-02-19Add PrID's for MIPS's 24K, 24KE, 34K and 74K cores.simonb
2007-10-17Merge the ppcoea-renovation branch to HEAD.garbled
2007-10-16Recognise the R2000A cpu as found in some pmaxen.simonb
2006-08-26Don't cast pointers using unsigned and/or int. Use intptr_t or uintptr_tmatt
2006-05-15Fix typo in MIPS3_SR_EIE.simonb
2005-12-20Add basic support for Alchemy Au1550 processor (CPU and devices).tron
2005-12-11merge ktrace-lwp.christos
2005-11-05Remove unused and incorrect MIPS_KSEG2_TO_PHYS() and MIPS_PHYS_TO_KSEG2()tsutsui