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path: root/sys/arch/mips/include/mipsNN.h
AgeCommit message (Expand)Author
2023-05-06s/Regiser/Register/ and s/regester/register/ in comments.andvar
2022-11-08Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.simonb
2020-08-02Document the PerfCntCrl registers (CP0 Register 25, Selects 0, 2, 4, 6).simonb
2020-07-31Rename MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT to MIPSNN_CFG4_MMU_SIZE_EXT.simonb
2020-07-31Bit definitions Config4 and Config5 registers.simonb
2020-07-26#define<tab>simonb
2020-06-13Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random positionsimonb
2020-06-13Use the correct config3 field name (ULRI) for UserLocal register issimonb
2016-07-11Change MIPS to use the common pmap code.matt
2011-08-16Add support for the MIPS DSP ASE (as a second PCU).matt
2006-03-20Added support for MIPS architecture revision 2.gdamore
2003-02-07Update to consistently use Broadcom GPL-compatible license on all SiByte code.cgd
2002-11-24Add the VI bit in config 0.simonb
2002-03-05Values related to the MIPS32/MIPS64 Privileged Resource Architecturesimonb