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mipsNN.h
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Author
2023-05-06
s/Regiser/Register/ and s/regester/register/ in comments.
andvar
2022-11-08
Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.
simonb
2020-08-02
Document the PerfCntCrl registers (CP0 Register 25, Selects 0, 2, 4, 6).
simonb
2020-07-31
Rename MIPSNN_CFG4_MMU_EXT_DEF_MMU_SIZE_EXT to MIPSNN_CFG4_MMU_SIZE_EXT.
simonb
2020-07-31
Bit definitions Config4 and Config5 registers.
simonb
2020-07-26
#define<tab>
simonb
2020-06-13
Move MIPSNN_CFG3_ULRI so that it doesn't appear in some random position
simonb
2020-06-13
Use the correct config3 field name (ULRI) for UserLocal register is
simonb
2016-07-11
Change MIPS to use the common pmap code.
matt
2011-08-16
Add support for the MIPS DSP ASE (as a second PCU).
matt
2006-03-20
Added support for MIPS architecture revision 2.
gdamore
2003-02-07
Update to consistently use Broadcom GPL-compatible license on all SiByte code.
cgd
2002-11-24
Add the VI bit in config 0.
simonb
2002-03-05
Values related to the MIPS32/MIPS64 Privileged Resource Architecture
simonb