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2023-06-24Fix typo in comment.msaitoh
2023-05-28s/Resture/Restore/ and s/restared/restarted/ in comments.andvar
2023-05-22Fix a commentskrll
2023-05-14Bump MAXTSIZ from 64MB to 128MB also for o32.he
This so that the rather large cc1 from gcc12 can be run. OK'ed by simonb@
2023-05-13fix typos in comments.andvar
2023-05-10mips: Use config_detach_children to reduce error branch bugs.riastradh
2023-05-06s/Regiser/Register/ and s/regester/register/ in comments.andvar
2023-04-28Pass local symbols relocations in both passes and provide the kobj_relocskrll
implementation visibility of these relocations. Currently all implementations resolve local symbol relocations in the first pass and simply skip them in the second. The RISC-V implementation will make use of this visiblity.
2023-03-28Add missing PRIuBUSSIZE to mips.nakayama
2023-03-21octrnm(4): Raise delay on startup.riastradh
According to CN50XX-HRM-V0.99E and CN78XX-HM-0.99E: The entropy is provided by the jitter of 125 of 128 free-running oscillators XORed into a 128-bit LFSR. The LFSR accumulates entropy over 81 cycles, after which it is fed into a SHA-1 engine. [...] The SHA-1 engine runs once every 81 cycles. [...] The hardware produces new 64-bit random number every 81 cycles. The last sentence means that we only need to wait 81 cycles _between_ consecutive SHA-1 outputs (which isn't relevant anyway because we reconfigure it into raw mode later), but the first two quotes might mean that we need to wait 81+81 cycles for the _first_ output to be produced on boot when running the self-test. Now, in this case, the self-test is run with the LFSR unhooked, by clearing the RNM_CTL_STATUS[ENT_EN] bit, so that SHA-1 is computed from a known input -- this is really just paranoia to make sure that _some_ functions of the device (which is conjured out of thin air at a fixed virtual address, with no firmware bindings to guide us) behave as we expect. And it's not clear if it really does take 81+81 cycles for the first SHA-1 output to appear when the LFSR isn't feeding into it anyway. But experimentally, delay of 81+81 cycles seems to work whereas a delay of only 81 cycles crashes. PR kern/57280 XXX pullup-10 XXX pullup-9
2023-03-01mips: Optimization: Omit needless membar when triggering softint.riastradh
When we are triggering a softint, it can't already hold any mutexes. So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is always done with atomic r/m/w, and we need not issue any explicit barrier between ci->ci_curlwp = softlwp and a potential load of mtx->mtx_owner in mutex_exit. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10
2023-02-26ci_data.cpu_kcpuset -> ci_kcpusetskrll
NFCI.
2023-02-25Convert some assignments into KASSERTs.skrll
l_md is zeroised by lwp_create with memset(&l2->l_startzero, 0, sizeof(*l2) - offsetof(lwp_t, l_startzero));
2023-02-23mips: Add missing barriers in cpu_switchto.riastradh
Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10
2023-02-20mips/asm.h: Make membar macros conditional on MULTIPROCESSOR.riastradh
For !MULTIPROCESSOR, define them to be empty or nop as appropriate.
2023-02-19Adjust userspace comments in db_read_bytes() and db_write_bytes() tosimonb
match current reality.
2023-02-19Only copyin/copyout from and to user addresses.mlelstv
2023-02-13mips/asm.h: Cite source for Cavium sync plunger business.riastradh
2023-01-31fix few typos in comments.andvar
2022-11-08Fix tyop in __BITS for the MIPSNN_MTI_CFG7_PREF_MASK macro.simonb
2022-10-26ddb/db_active.h: New home for extern db_active.riastradh
This can be included unconditionally, and db_active can then be queried unconditionally; if DDB is not in the kernel, then db_active is a constant zero. Reduces need for #include opt_ddb.h, #ifdef DDB.
2022-10-26MI PMAP hardware page table walker support.skrll
This is based on code given to me by Matt Thomas a long time ago with many updates and bugs fixes from me.
2022-10-23Fix build from previousskrll
2022-10-23Trailing whitespace.skrll
2022-09-29Remove unnecessary include of <sys/malloc.h>.skrll
2022-09-29Trailing whitespaceskrll
2022-09-25s/inerrupt/interrupt/ and s/intrrupt/interrupt/ in comments.andvar
2022-09-25Rename pmap_segtab_t *stp to stb for consistency with a futureskrll
pmap_pdetab_t *ptb. pmap_pdetab_t *ptp would be far too confusing. NFC. Same code before and after.
2022-09-18Eliminate use of IFF_OACTIVE.thorpej
2022-09-18Eliminate use of IFF_OACTIVE.thorpej
2022-08-20sbmac_start(): Replace "IF_DEQUEUE() -> IF_PREPEND() on failure" withthorpej
"IF_POLL() -> IF_DEQUEUE() on success".
2022-08-16Provide pci_intr_setattrskrll
2022-07-26s/functin/function/ in copy pasted comment.andvar
2022-07-20mips: Fix cpuids synchronization at boot.riastradh
2022-07-07Add PRIuVSIZEmartin
2022-06-18fix typos in word "functions" in comments, mainly s/fuctions/functions/.andvar
2022-06-03fix folloing->following typos in more files.andvar
also s/begginning/beginning/.
2022-05-31fix various typos in comments, documentation and messages.andvar
2022-05-24fix various typos in comment, documentation and log messages.andvar
2022-05-23s/controll/control/ in comments.andvar
2022-05-04s/entires/entries/andvar
2022-04-21mips/cavium: Take advantage of Octeon's guaranteed r/rw ordering.riastradh
2022-04-17fix various typos in comments.andvar
2022-04-09mips: Convert lock.h to membar_release/acquire.riastradh
2022-04-09mips/rmixl: Insert appropriate membars around IPIs.riastradh
2022-04-09mips/cavium: Insert appropriate membars around IPIs.riastradh
2022-04-09mips/rmi: Hack to get XLSATX64.MP kernel building again.riastradh
Using <mips/asm.h> in a .c file is kinda grody but CALLFRAME_SIZ doesn't seem to be defined anywhere else. Not sure how this was ever supposed to work...
2022-04-08fix various typos, mainly in comments, but also log messages, docs, game text.andvar
2022-03-28sys: Split struct device into a private device_impl.h.riastradh
Include this only inside autoconf itself, and a few files that abuse autoconf in ways I can't confidently make easy fixes for. XXX kernel ABI change requires bump -- no more use of struct device internals allowed, previously done by some drivers
2022-03-26mips/cavium: Simplify membars around interrupt establishment.riastradh
Previously I used xc_barrier to ensure the initialization of the struct octeon_intrhand was witnessed on all CPUs before publishing it, in order to avoid needing any barrier on the usage side to be issued by the interrupt handler. But there's no need to avoid atomic_load_consume at time of interrupt: on MIPS it's the same as atomic_load_relaxed anyway, so there's no additional memory barrier cost here.