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2023-06-24Fix typo in comment.msaitoh
2023-06-19Fix typo. unknwon -> unknownmsaitoh
2023-05-27fix word endings toin -> tion in comments.andvar
2023-05-10powerpc: Use config_detach_children to reduce error branch bugs.riastradh
2023-04-28Pass local symbols relocations in both passes and provide the kobj_relocskrll
implementation visibility of these relocations. Currently all implementations resolve local symbol relocations in the first pass and simply skip them in the second. The RISC-V implementation will make use of this visiblity.
2023-04-17Trailing whitespaceskrll
2023-04-17KNF.skrll
2023-04-13powerpc/ddb: Fix one more load to use db_read_bytes.riastradh
Fix some typos in crash(8) comments too. XXX pullup-8 XXX pullup-9 XXX pullup-10
2023-04-12powerpc/ddb: Use db_read_bytes, not direct pointer access.riastradh
Mark some powerpc-variant ifdefs with XXX crash(8), not sure yet what to do about them. XXX pullup-8 XXX pullup-9 XXX pullup-10
2023-04-12crash(8): Add powerpc support.riastradh
XXX pullup-8 XXX pullup-9 XXX pullup-10
2023-04-07Spaces to TABskrll
2023-03-01powerpc: Optimization: Omit needless membar when triggering softint.riastradh
When we are triggering a softint, it can't already hold any mutexes. So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is always done with atomic r/m/w, and we need not issue any explicit barrier between ci->ci_curlwp = softlwp and a potential load of mtx->mtx_owner in mutex_exit. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10
2023-02-23powerpc: Add missing barriers in cpu_switchto.riastradh
Details in comments. PR kern/57240 XXX pullup-8 XXX pullup-9 XXX pullup-10
2022-12-24s/Reqest/Request/ and adding apostrophe for don't and didn't in comments.andvar
2022-12-14if we have the ROM font, make it available to wsdisplaymacallan
needs testing on non-macppc
2022-12-12Move the last remaining kernel printf to ofprint.martin
2022-12-10Move some output to DEBUG-only statemartin
2022-12-10Convert more kernel printfs that might happen very early (before kernelmartin
console is usable) to ofprint.
2022-12-06convert more seriously early output to ofprintmacallan
regular console output needs more of the kernel in working order now, and this stuff happ0ens long before the banner
2022-12-05Do not bother to set PSL_SE in l_md.md_flags - it is not checked anywhere.martin
2022-12-05Do not copy l_md to the new lwp in cpu_lwp_fork - as discussed onmartin
tech-kern we do not want the child to inherit any of the flags in there.
2022-11-24in ofprint() only append \r if the last character is \nmacallan
2022-11-24move ofprint() to powerpc/ofw_machdep.c and make it officialmacallan
now that console output uses locks it needs more of the kernel to function, so for now use direct OF calls for earliest debug output
2022-11-15remove workaround for old clang - it's not needed anymore and caused problemsmacallan
elsewhere
2022-11-02fix various typos in comments and messages.andvar
2022-10-26ddb/db_active.h: New home for extern db_active.riastradh
This can be included unconditionally, and db_active can then be queried unconditionally; if DDB is not in the kernel, then db_active is a constant zero. Reduces need for #include opt_ddb.h, #ifdef DDB.
2022-10-26MI PMAP hardware page table walker support.skrll
This is based on code given to me by Matt Thomas a long time ago with many updates and bugs fixes from me.
2022-10-15DHT Walnut: Fix failure to attach on-board pdcide(4) for cold boot.rin
U-Boot seems to initialize pdcide(4) to compatible mode. Therefore, we need to reinitialize it to native-PCI mode in pci_conf_hook(). Otherwise, we will fail to configure IO registers for native-PCI mode during PCI_NETBSD_CONFIGURE.
2022-10-12fix few typos in comments.andvar
2022-10-05ppc4xx_tlb_enter: One more style sync. No binary changes.rin
Use hi and lo instead of th and tl for TLBHI and TLBLO, respectively, as done for other functions in pmap.c.
2022-10-05Use %[foo], %[bar], ... instead of %0, %1, ... for asm codes.rin
Unify variable names if possible. No binary changes.
2022-10-05Minor style fixes to asm codes. No binary changes.rin
2022-10-05copy{in,out}str: As a tiny optimization, drop redundant mtpid.rin
No regression for ATF on 405. 403 seems to work fine.
2022-10-04copy{in,out}str: Consistently use tmp as scratch register. NFC.rin
2022-10-04copy{in,out}str: "insn[TAB]operands;" for inline asm codes.rin
2022-10-04copy{in,out}str: Style sync with copy{in,out}. No binary changes.rin
2022-10-04copy{in,out}{,str}: Drop needless dcbst.rin
Data cache is purely physical for 40[53] with 16KB pages, and therefore no need to flush cache before context switch. This significantly improves copy{in,out} against small data; for example, bytebench on DHT becomes: -Pipe Throughput 12440.0 8826.1 7.1 +Pipe Throughput 12440.0 18364.8 14.8 No performance/ATF regression observed on 405. 403 boots successfully into multiuser mode, and builds some packages.
2022-10-03copy{in,out}str: Add cr0 and ctr to list of clobbered registers.rin
2022-10-03copy{in,out}str: Consistently use uaddr instead of udaddr.rin
Note that we use kaddr, not kdaddr, for kernel data address.
2022-10-03copy{in,out}str: Tidy up inline asm's:rin
- Use %[foo], %[bar], ... instead of %0, %1, ... - One instruction per line. - Paragraph grouped instructions. - Fix wrong comments. No binary changes.
2022-09-25Rename pmap_segtab_t *stp to stb for consistency with a futureskrll
pmap_pdetab_t *ptb. pmap_pdetab_t *ptp would be far too confusing. NFC. Same code before and after.
2022-09-20Typo in comment. No binary changes.rin
2022-09-20stfs{,x}{,u}: Switch to conversion algorithm specified by Power ISA.rin
The ISA specifies algorithm for most bit patterns in double format, that are not representable in float. I believe that sane people do not rely on such a specification detail, but *REAL* programmers may utilize it ;) Instead of complicating fpu_explode(), single-purpose helper function, fpu_to_single(), is introduced. See comment therein for more details.
2022-09-18Eliminate use of IFF_OACTIVE.thorpej
2022-09-18Eliminate use of IFF_OACTIVE.thorpej
2022-09-15fnm{add,sub}{,s}: Do not negate NaN.rin
2022-09-15fpu_execute(): Use FR() macro. No binary changes.rin
2022-09-14Fix logic for FPSCR[OX]; set FPSCR[FI] (and therefore FPSCR[XX]).rin
2022-09-14Fix logic for FPSCR[UX]:rin
- Correct FPSCR[FPRF] field when round to 0.0 or 0.0f. - Simplify.
2022-09-13fesetexceptflag(): Set FE_ALL_INVALID instead of FE_ALL_EXCEPT forrin
FE_INVALID. Taken from FreeBSD: https://cgit.freebsd.org/src/commit/lib/msun/powerpc/fenv.h?id=e7bd4f846f0c9185aebfd3d116bb78ab137280fa > [POWERPC] msun: fix incorrect flag in fesetexceptflag > Fix incorrect mask being used when FE_INVALID bit is wanted by user. > The problem was noticed thanks to msun fenv tests. > > Reviewed by: jhibbits, luporl > Sponsored by: Eldorado Research Institute (eldorado.org.br) > Differential Revision: https://reviews.freebsd.org/D27201 No regression for full ATF on both real and emulated FPU. XXX Import some tests from FreeBSD's lib/msun/tests.