| Age | Commit message (Collapse) | Author |
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implementation visibility of these relocations.
Currently all implementations resolve local symbol relocations in the first
pass and simply skip them in the second. The RISC-V implementation will
make use of this visiblity.
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Fix some typos in crash(8) comments too.
XXX pullup-8
XXX pullup-9
XXX pullup-10
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Mark some powerpc-variant ifdefs with XXX crash(8), not sure yet what
to do about them.
XXX pullup-8
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XXX pullup-8
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When we are triggering a softint, it can't already hold any mutexes.
So any path to mutex_exit(mtx) must go via mutex_enter(mtx), which is
always done with atomic r/m/w, and we need not issue any explicit
barrier between ci->ci_curlwp = softlwp and a potential load of
mtx->mtx_owner in mutex_exit.
PR kern/57240
XXX pullup-8
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Details in comments.
PR kern/57240
XXX pullup-8
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needs testing on non-macppc
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console is usable) to ofprint.
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regular console output needs more of the kernel in working order now, and this
stuff happ0ens long before the banner
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tech-kern we do not want the child to inherit any of the flags in there.
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now that console output uses locks it needs more of the kernel to function, so
for now use direct OF calls for earliest debug output
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elsewhere
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This can be included unconditionally, and db_active can then be
queried unconditionally; if DDB is not in the kernel, then db_active
is a constant zero. Reduces need for #include opt_ddb.h, #ifdef DDB.
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This is based on code given to me by Matt Thomas a long time ago with
many updates and bugs fixes from me.
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U-Boot seems to initialize pdcide(4) to compatible mode. Therefore, we
need to reinitialize it to native-PCI mode in pci_conf_hook(). Otherwise,
we will fail to configure IO registers for native-PCI mode during
PCI_NETBSD_CONFIGURE.
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Use hi and lo instead of th and tl for TLBHI and TLBLO, respectively,
as done for other functions in pmap.c.
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Unify variable names if possible. No binary changes.
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No regression for ATF on 405. 403 seems to work fine.
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Data cache is purely physical for 40[53] with 16KB pages, and therefore
no need to flush cache before context switch.
This significantly improves copy{in,out} against small data; for example,
bytebench on DHT becomes:
-Pipe Throughput 12440.0 8826.1 7.1
+Pipe Throughput 12440.0 18364.8 14.8
No performance/ATF regression observed on 405. 403 boots successfully
into multiuser mode, and builds some packages.
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Note that we use kaddr, not kdaddr, for kernel data address.
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- Use %[foo], %[bar], ... instead of %0, %1, ...
- One instruction per line.
- Paragraph grouped instructions.
- Fix wrong comments.
No binary changes.
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pmap_pdetab_t *ptb. pmap_pdetab_t *ptp would be far too confusing.
NFC. Same code before and after.
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The ISA specifies algorithm for most bit patterns in double format, that
are not representable in float. I believe that sane people do not rely on
such a specification detail, but *REAL* programmers may utilize it ;)
Instead of complicating fpu_explode(), single-purpose helper function,
fpu_to_single(), is introduced. See comment therein for more details.
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- Correct FPSCR[FPRF] field when round to 0.0 or 0.0f.
- Simplify.
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FE_INVALID. Taken from FreeBSD:
https://cgit.freebsd.org/src/commit/lib/msun/powerpc/fenv.h?id=e7bd4f846f0c9185aebfd3d116bb78ab137280fa
> [POWERPC] msun: fix incorrect flag in fesetexceptflag
> Fix incorrect mask being used when FE_INVALID bit is wanted by user.
> The problem was noticed thanks to msun fenv tests.
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> Reviewed by: jhibbits, luporl
> Sponsored by: Eldorado Research Institute (eldorado.org.br)
> Differential Revision: https://reviews.freebsd.org/D27201
No regression for full ATF on both real and emulated FPU.
XXX
Import some tests from FreeBSD's lib/msun/tests.
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