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lockcount-9.3
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NetBSD fork for lockdoc analysis
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specialreg.h
Age
Commit message (
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Author
2023-04-11
Fix compile error.
msaitoh
2023-04-11
Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.
msaitoh
2023-03-25
s/Predective/Predictive/ and s/dedected/detected/ in comments.
andvar
2023-02-17
Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.
msaitoh
2023-02-14
Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.
msaitoh
2022-12-30
Fix comment.
msaitoh
2022-12-30
Update definitions from the latest Intel SDM.
msaitoh
2022-12-27
Use __BIT(). Add comment. Whitespace. No functional change.
msaitoh
2022-11-21
Update AMD CPUID Fn8000_001b
msaitoh
2022-11-16
Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.
msaitoh
2022-11-16
Add CPUID Fn8000_0021 AMD Extended Features Identification 2.
msaitoh
2022-11-16
Add Some definitions from AMD APM:
msaitoh
2022-10-19
Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34.
msaitoh
2022-10-12
Add CPUID Fn8000_001e Processor Topology Information.
msaitoh
2022-10-06
Update some AMD CPUID bits:
msaitoh
2022-06-15
Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.
msaitoh
2022-06-13
Add top-down slots event bit of architectural performance monitoring leaf.
msaitoh
2022-02-01
s/shareing/sharing/. No functional change.
msaitoh
2022-01-29
Add Intel Hybrid Information Enumeration (CPUID Fn0000_001a).
msaitoh
2022-01-17
fix typos in comments, mainly s/foward/forward/.
andvar
2022-01-15
Add Some definitions from AMD APM:
msaitoh
2022-01-15
Whitespace. No functional change.
msaitoh
2022-01-15
Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax.
msaitoh
2022-01-15
No functional change.
msaitoh
2022-01-14
Add Architectural LBR and Linear Address Masking.
msaitoh
2022-01-14
Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH".
msaitoh
2022-01-13
Add some CPUID bits from the latest Intel SDM.
msaitoh
2022-01-13
Use __BIT(). KNF. No functional change.
msaitoh
2021-09-30
Print CPUID_PBE (Pending Break Enable) with "PBE".
msaitoh
2021-07-10
Add some definitions from Intel SDM:
msaitoh
2020-11-24
Add some definitions from the latest Intel SDM:
msaitoh
2020-09-07
Fix printb string for LA57
jakllsch
2020-09-07
Add CPUID(EAX=07H, ECX=0) ECX bit 16 LA57 from maxv.
msaitoh
2020-09-05
x86: fix several CPUID flags
maxv
2020-09-04
Add a few more CPUID flags.
maxv
2020-08-05
Add new fields here and there.
maxv
2020-07-20
Revert previous, to unbreak the build (NVMM declares the macro too).
maxv
2020-07-19
add definition for MSR_IA32_FEATURE_CONTROL, just for information
jdolecek
2020-06-18
style and fix typo
maxv
2020-06-10
Add SRBDS_CTRL bit.
msaitoh
2020-06-01
Add some definitions from the latest Intel SDM plus small fix:
msaitoh
2020-05-28
Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.
msaitoh
2020-05-01
- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.
msaitoh
2020-04-25
Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVM
bouyer
2020-04-24
- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".
msaitoh
2020-04-06
Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.
msaitoh
2020-04-06
CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007
msaitoh
2020-04-01
Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)
msaitoh
2019-11-17
Add the following bit definitions from the latest Intel SDM:
msaitoh
2019-11-12
Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).
maxv
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