summaryrefslogtreecommitdiff
path: root/sys/arch/x86/include/specialreg.h
AgeCommit message (Expand)Author
2023-04-11Fix compile error.msaitoh
2023-04-11Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.msaitoh
2023-03-25s/Predective/Predictive/ and s/dedected/detected/ in comments.andvar
2023-02-17Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.msaitoh
2023-02-14Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.msaitoh
2022-12-30Fix comment.msaitoh
2022-12-30Update definitions from the latest Intel SDM.msaitoh
2022-12-27Use __BIT(). Add comment. Whitespace. No functional change.msaitoh
2022-11-21Update AMD CPUID Fn8000_001bmsaitoh
2022-11-16Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.msaitoh
2022-11-16Add CPUID Fn8000_0021 AMD Extended Features Identification 2.msaitoh
2022-11-16Add Some definitions from AMD APM:msaitoh
2022-10-19Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34.msaitoh
2022-10-12Add CPUID Fn8000_001e Processor Topology Information.msaitoh
2022-10-06Update some AMD CPUID bits:msaitoh
2022-06-15Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.msaitoh
2022-06-13Add top-down slots event bit of architectural performance monitoring leaf.msaitoh
2022-02-01s/shareing/sharing/. No functional change.msaitoh
2022-01-29Add Intel Hybrid Information Enumeration (CPUID Fn0000_001a).msaitoh
2022-01-17fix typos in comments, mainly s/foward/forward/.andvar
2022-01-15Add Some definitions from AMD APM:msaitoh
2022-01-15Whitespace. No functional change.msaitoh
2022-01-15Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax.msaitoh
2022-01-15No functional change.msaitoh
2022-01-14Add Architectural LBR and Linear Address Masking.msaitoh
2022-01-14Both Intel and AMD says the name of CPUID 0x01 %edx bit 19 is "CLFSH".msaitoh
2022-01-13Add some CPUID bits from the latest Intel SDM.msaitoh
2022-01-13 Use __BIT(). KNF. No functional change.msaitoh
2021-09-30Print CPUID_PBE (Pending Break Enable) with "PBE".msaitoh
2021-07-10Add some definitions from Intel SDM:msaitoh
2020-11-24Add some definitions from the latest Intel SDM:msaitoh
2020-09-07Fix printb string for LA57jakllsch
2020-09-07 Add CPUID(EAX=07H, ECX=0) ECX bit 16 LA57 from maxv.msaitoh
2020-09-05x86: fix several CPUID flagsmaxv
2020-09-04Add a few more CPUID flags.maxv
2020-08-05Add new fields here and there.maxv
2020-07-20Revert previous, to unbreak the build (NVMM declares the macro too).maxv
2020-07-19add definition for MSR_IA32_FEATURE_CONTROL, just for informationjdolecek
2020-06-18style and fix typomaxv
2020-06-10 Add SRBDS_CTRL bit.msaitoh
2020-06-01Add some definitions from the latest Intel SDM plus small fix:msaitoh
2020-05-28Add AMD MSR_DE_CFG's bit 1 as DE_CFG_LFENCE_SERIALIZE.msaitoh
2020-05-01- Add AMD INVLPGB/TLBSYNC hypervisor enable in VMCB and TLBSYNC intercept bit.msaitoh
2020-04-25Merge the bouyer-xenpvh branch, bringing in Xen PV drivers support under HVMbouyer
2020-04-24- AMD CPUID Fn8000_000a %edx bit 20 is "SPEC_CTRL".msaitoh
2020-04-06 Rename CPUID_APM_TSC to CPUID_APM_ITSC. No functional change.msaitoh
2020-04-06 CPUID Fn00000001 %edx bit 8 is printed as "TSC", so rename CPUID Fn8000_0007msaitoh
2020-04-01Add AVX512_VP2INTERSECT, SERIALIZE and TSXLDTRK(TSX suspend load addr tracking)msaitoh
2019-11-17Add the following bit definitions from the latest Intel SDM:msaitoh
2019-11-12Mitigation for CVE-2019-11135: TSX Asynchronous Abort (TAA).maxv