| Age | Commit message (Collapse) | Author |
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In fpu_kern_enter, make sure all the MXCSR exception status bits are
set when we start using the FPU, so that instructions which exhibit
MCDT are unaffected by it.
While here, zero all the other FPU registers in fpu_kern_enter.
In principle we could skip this step on future CPUs that fix the MCDT
bug, but there's probably not much benefit -- workloads that do a lot
of crypto in the kernel are probably better off using
kthread_fpu_enter or WQ_FPU to skip the fpu_kern_enter/leave cycles
in the first place.
For details, see:
https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/mxcsr-configuration-dependent-timing.html
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PR kern/57197
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- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface).
- Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware
Feedback Notification support.
- Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD.
- Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS.
- Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts).
- Add CPUID Fn0000_0007 %edx bit 1 RTM_ALWAYS_ABORT.
- Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT.
- Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16.
- Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16.
- Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE.
- Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8.
- Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 0 PSFD.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 3 DDPD_U.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 4 BHI_CTRL.
- Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 5 MCDT_NO.
- Modify comment. Both Intel and AMD support CPUID Fn0000000b.
- Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD.
- Modify comment. Hybrid Information -> Native Model ID Information.
- Add CPUID Fn0000_001d Tile Information.
- Add CPUID Fn0000_001e TMUL Information.
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- Add IbsFetchCtlExtd and IbsOpData4.
- Fix typo (lbs -> Ibs).
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- Add CPUID Fn8000_0007 %eax RAS capabilities.
- Add CPUID Fn8000_001b Instruction-Based Sampling capabilities.
- Add BTC_NO, ROGPT, RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam,
VirtualTomMsr, bsVirtGuest, SmtProtection, vsmCommPageMSR and
NestedVirtSnpMsr.
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- Rename FSREP_MOV to FSRM.
- Add Memory Bandwidth Enforcement (MBE)
- Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN.
- Add Collaborative Processor Performance Control (CPPC).
- Add HOST_MCE_OVERRIDE.
- Add some unknown bits as Bxx.
- Add comments.
- Use __BIT().
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This creates a special pmap, efi_runtime_pmap, which avoids setting
PTE_U but allows mappings to lie in what would normally be user VM --
this way we don't fall afoul of SMAP/SMEP when executing EFI runtime
services from CPL 0. SVS does not apply to the EFI runtime pmap.
The mechanism is intended to work with either physical addressing or
virtual addressing; currently the bootloader does physical addressing
but in principle it could be modified to do virtual addressing
instead, if it allocated virtual pages, assigned them in the memory
map, and issued RT->SetVirtualAddressMap.
Not sure pmap_activate_sync and pmap_deactivate_sync are correct,
need more review from an x86 wizard.
If this causes fallout, it can be disabled temporarily without
reverting anything by just making efi_runtime_init return immediately
without doing anything, or by removing options EFI_RUNTIME.
amd64-only for now pending type fixes and testing on i386.
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There has been no objection for three years.
https://mail-index.netbsd.org/port-amd64/2019/09/22/msg003012.html
Implemented by nonaka@n.o, updated by me.
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This makes pmap_resident_count and pmap_wired_count out-of-line
functions instead of inline. No functional change intended
otherwise.
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This way pmap.h only contains the MD definition of the MI pmap(9)
API, which loads of things in the kernel rely on, so changing x86
pmap internals no longer requires recompiling the entire kernel every
time.
Callers needing these internals must now use machine/pmap_private.h.
Note: This is not x86/pmap_private.h because it contains three parts:
1. CPU-specific (different for i386/amd64) definitions used by...
2. common definitions, including Xenisms like xpmap_ptetomach,
further used by...
3. more CPU-specific inlines for pmap_pte_* operations
So {amd64,i386}/pmap_private.h defines 1, includes x86/pmap_private.h
for 2, and then defines 3. Maybe we should split that out into a new
pmap_pte.h to reduce this trouble.
No functional change intended, other than that some .c files must
include machine/pmap_private.h when previously uvm/uvm_pmap.h
polluted the namespace with pmap internals.
Note: This migrates part of i386/pmap.h into i386/vmparam.h --
specifically the parts that are needed for several constants defined
in vmparam.h:
VM_MAXUSER_ADDRESS
VM_MAX_ADDRESS
VM_MAX_KERNEL_ADDRESS
VM_MIN_KERNEL_ADDRESS
Since i386 needs PDP_SIZE in vmparam.h, I added it there on amd64
too, just to keep things parallel.
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machine/pte.h already used outside sys/arch, so let's make it the
primary thing and make sure to use x86/pte.h only as a subroutine.
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- pl[1-4]_i -> x86/pte.h
- pl_i, pl_i_roundup, ptp_va2o -> x86/pmap.c
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No functional change intended.
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when no interrupt are pending. So add an extra ih_pending field
to struct intrhand, which is incremeted when the handler is not called because
of IPL level and reset to 0 when called. Check this in Xen's resume
assembly to call only handlers that are really pending.
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It is, and always has been, the caller's responsibility to ensure the
lock is initialized before it can be used -- otherwise the memory
could hold garbage; it is nonsensical to even attempt locking
operations on it before initialization.
So there's no need to issue explicit barriers here. The barrier
seems to have been introduced in sys/arch/alpha/alpha/lock_machdep.c
rev. 1.1 (since moved to inline asm in alpha/include/lock.h) and then
copied & pasted into several other architectures.
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everywhere.
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- CPUID Fn80000001 %ecx bit 30 AddrMaskExt.
- CPUID Fn80000008 %ebx bit 13 INT_WBINVD.
- CPUID Fn80000008 %ebx bit 19 IbrsSameMode.
- CPUID Fn80000008 %ebx bit 20 EferLmsleUnsupported.
- CPUID Fn80000008 %ebx bit 28 PSFD.
- CPUID Fn80000008 %edx bit 30 as "B30". Not documented.
- CPUID Fn8000001f %eax bit 8 SecureTSC.
- CPUID Fn8000001f %eax bit 24 VmsaRegProt.
- Tested by nonaka@.
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