summaryrefslogtreecommitdiff
path: root/sys/arch/x86/include
AgeCommit message (Collapse)Author
2023-04-11Fix compile error.msaitoh
2023-04-11Add CPUID 0x07 %ecx bit 24 BUS_LOCK_DETECT.msaitoh
2023-03-25s/Predective/Predictive/ and s/dedected/detected/ in comments.andvar
2023-02-25x86: Mitigate MXCSR Configuration Dependent Timing in kernel FPU use.riastradh
In fpu_kern_enter, make sure all the MXCSR exception status bits are set when we start using the FPU, so that instructions which exhibit MCDT are unaffected by it. While here, zero all the other FPU registers in fpu_kern_enter. In principle we could skip this step on future CPUs that fix the MCDT bug, but there's probably not much benefit -- workloads that do a lot of crypto in the kernel are probably better off using kthread_fpu_enter or WQ_FPU to skip the fpu_kern_enter/leave cycles in the first place. For details, see: https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/best-practices/mxcsr-configuration-dependent-timing.html
2023-02-17Add AMD CPUID Fn0000_0008 %ebx bit 3 INVLPGB.msaitoh
2023-02-14Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.msaitoh
2023-01-25x86/intr: Work around sleazy clockintr with a secret frame argument.riastradh
PR kern/57197
2022-12-30Fix comment.msaitoh
2022-12-30Update definitions from the latest Intel SDM.msaitoh
- Rename HW_FEEDBACK to HWI (Hardware Feedback Interface). - Add CPUID Fn0000_0006 %eax bit 24 IA32_THERM_INTERRUPT MSR bit 25 Hardware Feedback Notification support. - Add CPUID Fn0000_0007 %ecx bit 29 ENQCMD. - Add CPUID Fn0000_0007 %edx bit 1 SGX-KEYS. - Add CPUID Fn0000_0007 %edx bit 5 UINTR(User INTeRrupts). - Add CPUID Fn0000_0007 %edx bit 1 RTM_ALWAYS_ABORT. - Rename TSX_FORCE_ABORT to RTM_FORCE_ABORT. - Add CPUID Fn0000_0007 %edx bit 22 AMX_BF16. - Add CPUID Fn0000_0007 %edx bit 23 AVX512_FP16. - Add CPUID Fn0000_0007 %edx bit 24 AMX_TILE. - Add CPUID Fn0000_0007 %edx bit 25 AMX_INT8. - Add CPUID Fn0000_0007 sub-leaf 1 %edx bit 18 CET_SSS. - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 0 PSFD. - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 1 IPRED_CTRL. - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 2 RRSBA_CTRL. - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 3 DDPD_U. - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 4 BHI_CTRL. - Add CPUID Fn0000_0007 sub-leaf 2 %edx bit 5 MCDT_NO. - Modify comment. Both Intel and AMD support CPUID Fn0000000b. - Add CPUID Fn0000_000d sub-leaf 1 %eax bit 4 XFD. - Modify comment. Hybrid Information -> Native Model ID Information. - Add CPUID Fn0000_001d Tile Information. - Add CPUID Fn0000_001e TMUL Information.
2022-12-27Use __BIT(). Add comment. Whitespace. No functional change.msaitoh
2022-11-21Update AMD CPUID Fn8000_001bmsaitoh
- Add IbsFetchCtlExtd and IbsOpData4. - Fix typo (lbs -> Ibs).
2022-11-16Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.msaitoh
2022-11-16Add CPUID Fn8000_0021 AMD Extended Features Identification 2.msaitoh
2022-11-16Add Some definitions from AMD APM:msaitoh
- Add CPUID Fn8000_0007 %eax RAS capabilities. - Add CPUID Fn8000_001b Instruction-Based Sampling capabilities. - Add BTC_NO, ROGPT, RPMQUERY, VmplSSS, TscAuxVirt, VmgexitParam, VirtualTomMsr, bsVirtGuest, SmtProtection, vsmCommPageMSR and NestedVirtSnpMsr.
2022-10-19Add AMD cpuid Fn8000_000a x2AVIC, VNMI and IBSVIRT from APM Vol. 3 Rev. 3.34.msaitoh
2022-10-12Add CPUID Fn8000_001e Processor Topology Information.msaitoh
2022-10-06IOAPIC_ID_MASK is 8 bits these days. Fixes PR kern/54276.msaitoh
2022-10-06Update some AMD CPUID bits:msaitoh
- Rename FSREP_MOV to FSRM. - Add Memory Bandwidth Enforcement (MBE) - Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN. - Add Collaborative Processor Performance Control (CPPC). - Add HOST_MCE_OVERRIDE. - Add some unknown bits as Bxx. - Add comments. - Use __BIT().
2022-09-24x86: Support EFI runtime services.riastradh
This creates a special pmap, efi_runtime_pmap, which avoids setting PTE_U but allows mappings to lie in what would normally be user VM -- this way we don't fall afoul of SMAP/SMEP when executing EFI runtime services from CPL 0. SVS does not apply to the EFI runtime pmap. The mechanism is intended to work with either physical addressing or virtual addressing; currently the bootloader does physical addressing but in principle it could be modified to do virtual addressing instead, if it allocated virtual pages, assigned them in the memory map, and issued RT->SetVirtualAddressMap. Not sure pmap_activate_sync and pmap_deactivate_sync are correct, need more review from an x86 wizard. If this causes fallout, it can be disabled temporarily without reverting anything by just making efi_runtime_init return immediately without doing anything, or by removing options EFI_RUNTIME. amd64-only for now pending type fixes and testing on i386.
2022-09-15Verify checksum of the extended signature table.msaitoh
2022-09-13x86/pmap.h: Need machine/cpufunc.h for invlpg.riastradh
2022-09-07NetBSD/x86: Raise the number of interrupt sources per CPU from 32 to 56.knakahara
There has been no objection for three years. https://mail-index.netbsd.org/port-amd64/2019/09/22/msg003012.html Implemented by nonaka@n.o, updated by me.
2022-08-20x86: Move definition of struct pmap to pmap_private.h.riastradh
This makes pmap_resident_count and pmap_wired_count out-of-line functions instead of inline. No functional change intended otherwise.
2022-08-20x86: Split most of pmap.h into pmap_private.h or vmparam.h.riastradh
This way pmap.h only contains the MD definition of the MI pmap(9) API, which loads of things in the kernel rely on, so changing x86 pmap internals no longer requires recompiling the entire kernel every time. Callers needing these internals must now use machine/pmap_private.h. Note: This is not x86/pmap_private.h because it contains three parts: 1. CPU-specific (different for i386/amd64) definitions used by... 2. common definitions, including Xenisms like xpmap_ptetomach, further used by... 3. more CPU-specific inlines for pmap_pte_* operations So {amd64,i386}/pmap_private.h defines 1, includes x86/pmap_private.h for 2, and then defines 3. Maybe we should split that out into a new pmap_pte.h to reduce this trouble. No functional change intended, other than that some .c files must include machine/pmap_private.h when previously uvm/uvm_pmap.h polluted the namespace with pmap internals. Note: This migrates part of i386/pmap.h into i386/vmparam.h -- specifically the parts that are needed for several constants defined in vmparam.h: VM_MAXUSER_ADDRESS VM_MAX_ADDRESS VM_MAX_KERNEL_ADDRESS VM_MIN_KERNEL_ADDRESS Since i386 needs PDP_SIZE in vmparam.h, I added it there on amd64 too, just to keep things parallel.
2022-08-20x86: Forbid using x86/pte.h directly; use machine/pte.h.riastradh
machine/pte.h already used outside sys/arch, so let's make it the primary thing and make sure to use x86/pte.h only as a subroutine.
2022-08-20x86: Move pl*_i, pl_i_roundup, and ptp_va2o out of x86/pmap.h.riastradh
- pl[1-4]_i -> x86/pte.h - pl_i, pl_i_roundup, ptp_va2o -> x86/pmap.c
2022-08-20x86: Move struct vm_page_md to common x86/pmap.h.riastradh
2022-08-20x86: Split bootspace out of x86/pmap.h into new x86/bootspace.h.riastradh
2022-08-20x86: Move page attribute table bits to x86/pat.h.riastradh
2022-08-20x86/bootinfo.h: Add include guard.riastradh
2022-08-20machine/efi.h: Migrate common definitions to dev/efi/efi.h.riastradh
2022-08-20x86/efi.h: Assert size of struct efi_systbl.riastradh
2022-08-20arm/efi.h, x86/efi.h: Fix whitespace around RCS id.riastradh
No functional change intended.
2022-08-20x86/efi.h: Fix whitespace. No functional change intended.riastradh
2022-08-20machine/efi.h: Add more memory descriptor attributes.riastradh
2022-06-18fix typos in word "functions" in comments, mainly s/fuctions/functions/.andvar
2022-06-15Modify CPUID Fn0000000a %ebx's string. Add new string for %ecx.msaitoh
2022-06-13Add top-down slots event bit of architectural performance monitoring leaf.msaitoh
2022-05-24Some devices (e.g. ixg in MSI-X mode) don't to have their handlers calledbouyer
when no interrupt are pending. So add an extra ih_pending field to struct intrhand, which is incremeted when the handler is not called because of IPL level and reset to 0 when called. Check this in Xen's resume assembly to call only handlers that are really pending.
2022-04-04fix various typos, mainly in comments.andvar
2022-04-01Trailing whitespaceskrll
2022-03-12x86: Check for biglock leakage in interrupt handlers.riastradh
2022-02-12__cpu_simple_lock(9): Omit needless barriers in init.riastradh
It is, and always has been, the caller's responsibility to ensure the lock is initialized before it can be used -- otherwise the memory could hold garbage; it is nonsensical to even attempt locking operations on it before initialization. So there's no need to issue explicit barriers here. The barrier seems to have been introduced in sys/arch/alpha/alpha/lock_machdep.c rev. 1.1 (since moved to inline asm in alpha/include/lock.h) and then copied & pasted into several other architectures.
2022-02-01s/shareing/sharing/. No functional change.msaitoh
2022-01-29Add Intel Hybrid Information Enumeration (CPUID Fn0000_001a).msaitoh
2022-01-22Ensure bus_dmatag_subregion is called with an inclusive max_addrskrll
everywhere.
2022-01-17fix typos in comments, mainly s/foward/forward/.andvar
2022-01-15Add Some definitions from AMD APM:msaitoh
- CPUID Fn80000001 %ecx bit 30 AddrMaskExt. - CPUID Fn80000008 %ebx bit 13 INT_WBINVD. - CPUID Fn80000008 %ebx bit 19 IbrsSameMode. - CPUID Fn80000008 %ebx bit 20 EferLmsleUnsupported. - CPUID Fn80000008 %ebx bit 28 PSFD. - CPUID Fn80000008 %edx bit 30 as "B30". Not documented. - CPUID Fn8000001f %eax bit 8 SecureTSC. - CPUID Fn8000001f %eax bit 24 VmsaRegProt. - Tested by nonaka@.
2022-01-15Whitespace. No functional change.msaitoh
2022-01-15Move CPUID_CAPEX_FLAGS next to %eax because it's for %eax.msaitoh