summaryrefslogtreecommitdiff
path: root/sys/conf/files
AgeCommit message (Collapse)Author
2023-04-16Separate DesignWare watchdog driver and FDT glue.jmcneill
2022-12-28remove lingering strip(4) remnantsjakllsch
2022-12-19Create compat_100 module infrastructure now that we have branchedpgoyette
for NetBSD-10
2022-12-03Split the BMP280 / BME280 driver into common code and create I2C andbrad
SPI attachments.
2022-11-05Add driver for Cadence I2C controller.jmcneill
2022-10-28MI PMAP EFI_RUNTIME supportskrll
2022-07-24use defparam; noted by tnn@.mrg
2022-07-23make MAXLWP a real option that triggers rebuilds properly.mrg
2022-07-20drm: Use CPPFLAGS.drmkms in all local drm drivers too.riastradh
This way we don't pollute the NetBSD kernel namespace with all the Linux compat shim definitions needed to build drm, except for the local drm drivers that need the API.
2022-06-05bwfm(4) uses firmload.rjs
2022-05-07Add MODULAR_DEFAULT_VERBOSE option.rin
2022-03-24Add initial support for Intel GPIO chipsmanu
2022-02-16sys: Include files.acpica unconditionally.riastradh
This way acpica.h always exists unconditionally, so MI code can be conditional on NACPICA. It is not great to have such conditionals, but it's better to have #include "acpica.h" #ifdef NACPICA > 0 than to have #if defined(__i386__) || defined(__x86_64__) || defined(__arm__) #include "acpica.h" #endif #ifdef NACPICA > 0 and we can still grep for NACPICA to find places that could be factored better.
2022-01-17Re-factor and overhaul the "mcp23s17gpio" driver as "mcpgpio", andthorpej
add support for 8-bit and I2C variants of the chip: - MCP23008 / MCP23S08: 8-bit (I2C / SPI) - MCP23017 / MCP23S17: 16-bit (I2C / SPI) - MCP23018 / MCP23S18: 16-bit (I2C / SPI), open-drain outputs The MCP23x17 and MCP23x18 are essentially identical, software-wise; we merely report different GPIO pin capabilities (no push-pull output for MCP23x18). Also, remove the tri-state capability that was previously advertised by the old version of this driver; these chips have no way to put the pin into a HI-Z mode. All 3 I2C versions are supported, but the SPI front-end still only supports the MCP23S17 for now (SPI autoconfiguration needs an overhaul). mcp23s17gpio(4) remains present as a link to the new mcpgpio(4) man page. XXX Still to-do: FDT integration, interrupt suppoort. (File missed in prior commit.)
2022-01-03Add driver for DesignWare Ethernet Quality-of-Service controller.jmcneill
2022-01-01s/sytem/system/msaitoh
2021-12-07A driver and user land utility for the Sparkfun Serial Controlled Motorbrad
Driver module as illustrated here: https://www.sparkfun.com/products/13911 A SCMD module is a ARM SOC simular to a Arduino in front of a motor driver chip. The single SCMD module can control two motors and up to 16 additional modules can be chained together using an internal I2C bus. One can interface with the SCMD using tty uart commands, SPI or I2C. The driver in this commit adds a kernel driver for the I2C and SPI interfaces. The command line utility provides a set of convenience commands that support most of the functions of the SCMD and is able to use the tty uart mode, SPI user land or the included kernel driver in a uniform manor. The use of the SCMD module is mostly for small robots and the like, but it can control anything that is controllable by voltage.
2021-11-19ahcisata(4): Introduce AHCI_QUIRK_EXTRA_DELAY quirk for devices thatrin
need extra delays as done by AHCISATA_EXTRA_DELAY option. Enable this quirk for "C600/X79 AHCI". Also add commented out quirk entries for "Bay Trail SATA (AHCI)" and "Mobile AHCI SATA Controller", for which non-reproducible failures worked around by extra delays have been reported. 500 ms of delays inserted by these option/quirk may be too much. Add AHCISATA_EXTRA_DELAY_MS option to adjust number of delays in ms, like: ---- options AHCISATA_EXTRA_DELAY_MS=200 ---- Thanks prlw1@ and jun@ for testing!
2021-10-11add defflag for AHCISATA_EXTRA_DELAYjmcneill
2021-10-11defparam NMBCLUSTERS_MAX.msaitoh
2021-07-21Separate MI smbios interface from MD specific code.jmcneill
2021-06-01Fix not to do if_down() before reconnectyamaguchi
Almost network interface do not use if_down() even when there is no connectivity. So, pppoe(4) is also made be not used it. This behavior can be rollbacked by SPPP_IFDOWN_RECONNECT option.
2021-05-29Put the MSGBUFSIZE option in opt_param.h so that changes of its settingsimonb
in kernel config files will be picked up automatically without needing a "make clean". Added to opt_param.h since ports define their default MSGBUFSIZE settings in their <arch/include/param.h> (or equivalent).
2021-05-19Added a kernel option to change the number of processing packetsyamaguchi
at one pppoeintr()
2021-05-17Add a new link-aggregation pseudo interface named lagg(4)yamaguchi
- FreeBSD's lagg(4) based implementation - MP-safe and MP-scalable
2021-05-14Add a parameter to change keepalive interval in each PPPoE I/Fyamaguchi
2021-05-14Added SPPP_NORECV_TIME option to change pp_max_noreceiveyamaguchi
2021-05-14Introduce SPPP_KEEPALIVE_INTERVAL optionyamaguchi
to change the interval between LCP echo requests
2021-02-06defflag USBHIST_PRINTdbj
2021-01-16remove unused "_DIAGNOSTIC" option and opt_diagnostic.h.chs
note that this is unrelated to the widely used "DIAGNOSTIC" option.
2020-10-27move vmt(4) from MD to MI, and add support vmt on aarch64. tested on ↵ryo
ESXi-Arm Fling - move from sys/arch/x86/x86/{vmt.c,vmtreg.h,vmtvar.h} to sys/dev/vmt/{vmt_subr.c,vmtreg.h,vmtvar.h}, and split the attach part of the cpufeaturebus and fdt - add aarch64 vmware backdoor op - add include guard to vmt{reg,var}.h - Yet there is still some little-endian dependency. it needs to be fixed in order to work properly on aarch64eb
2020-09-27Wups, forgot to commit this with vether.roy
2020-08-20[ozaki-r] Changes to the kernel core for wireguardriastradh
2020-08-01Remove references to BRIDGE_IPF, it is now compiled in by default.maxv
2020-07-25New ChaCha API in kernel.riastradh
This will enable us to adopt MD vectorized implementations of ChaCha.
2020-07-25Convert ieee80211_crypto_ccmp.c to new aes_ccm API.riastradh
This will make it easier to provide better hardware acceleration without fpu enabling/disabling overhead for each block of data.
2020-06-29New cgd cipher adiantum.riastradh
Adiantum is a wide-block cipher, built out of AES, XChaCha12, Poly1305, and NH, defined in Paul Crowley and Eric Biggers, `Adiantum: length-preserving encryption for entry-level processors', IACR Transactions on Symmetric Cryptology 2018(4), pp. 39--61. Adiantum provides better security than a narrow-block cipher with CBC or XTS, because every bit of each sector affects every other bit, whereas with CBC each block of plaintext only affects the following blocks of ciphertext in the disk sector, and with XTS each block of plaintext only affects its own block of ciphertext and nothing else. Adiantum generally provides much better performance than constant-time AES-CBC or AES-XTS software do without hardware support, and performance comparable to or better than the variable-time (i.e., leaky) AES-CBC and AES-XTS software we had before. (Note: Adiantum also uses AES as a subroutine, but only once per disk sector. It takes only a small fraction of the time spent by Adiantum, so there's relatively little performance impact to using constant-time AES software over using variable-time AES software for it.) Adiantum naturally scales to essentially arbitrary disk sector sizes; sizes >=1024-bytes take the most advantage of Adiantum's design for performance, so 4096-byte sectors would be a natural choice if we taught cgd to change the disk sector size. (However, it's a different cipher for each disk sector size, so it _must_ be a cgd parameter.) The paper presents a similar construction HPolyC. The salient difference is that HPolyC uses Poly1305 directly, whereas Adiantum uses Poly1395(NH(...)). NH is annoying because it requires a 1072-byte key, which means the test vectors are ginormous, and changing keys is costly; HPolyC avoids these shortcomings by using Poly1305 directly, but HPolyC is measurably slower, costing about 1.5x what Adiantum costs on 4096-byte sectors. For the purposes of cgd, we will reuse each key for many messages, and there will be very few keys in total (one per cgd volume) so -- except for the annoying verbosity of test vectors -- the tradeoff weighs in the favour of Adiantum, especially if we teach cgd to do >>512-byte sectors. For now, everything that Adiantum needs beyond what's already in the kernel is gathered into a single file, including NH, Poly1305, and XChaCha12. We can split those out -- and reuse them, and provide MD tuned implementations, and so on -- as needed; this is just a first pass to get Adiantum implemented for experimentation.
2020-06-29cgd(4): Switch from legacy rijndael API to new aes API.riastradh
2020-06-29Rework AES in kernel to finally address CVE-2005-1797.riastradh
1. Rip out old variable-time reference implementation. 2. Replace it by BearSSL's constant-time 32-bit logic. => Obtained from commit dda1f8a0c46e15b4a235163470ff700b2f13dcc5. => We could conditionally adopt the 64-bit logic too, which would likely give a modest performance boost on 64-bit platforms without AES-NI, but that's a bit more trouble. 3. Select the AES implementation at boot-time; allow an MD override. => Use self-tests to verify basic correctness at boot. => The implementation selection policy is rather rudimentary at the moment but it is isolated to one place so it's easy to change later on. This (a) plugs a host of timing attacks on, e.g., cgd, and (b) paves the way to take advantage of CPU support for AES -- both things we should've done a decade ago. Downside: Computing AES takes 2-3x the CPU time. But that's what hardware support will be coming for. Rudimentary measurement of performance impact done by: mount -t tmpfs tmpfs /tmp dd if=/dev/zero of=/tmp/disk bs=1m count=512 vnconfig -cv vnd0 /tmp/disk cgdconfig -s cgd0 /dev/vnd0 aes-cbc 256 < /dev/zero dd if=/dev/rcgd0d of=/dev/null bs=64k dd if=/dev/zero of=/dev/rcgd0d bs=64k The AES-CBC encryption performance impact is closer to 3x because it is inherently sequential; the AES-CBC decryption impact is closer to 2x because the bitsliced AES logic can process two blocks at once. Discussed on tech-kern: https://mail-index.NetBSD.org/tech-kern/2020/06/18/msg026505.html
2020-06-07Add fault(4).maxv
2020-05-20i.MX support merged into GENERIC kernel.hkenken
2020-04-22Make crypto/rijindael optional again as cprng_strong does no longerrin
depend on it. Dependency is explicitly declared in files.foo if a component requires it.
2020-04-15Introduce POOL_NOCACHE, simple option to cancel pool_caches and go directlymaxv
to the pool layer. It is taken out of POOL_QUARANTINE. Advertise POOL_NOCACHE for kMSan rather than POOL_QUARANTINE. With kMSan we are only interested in the no-caching effect, not the quarantine. This reduces memory pressure on kMSan kernels.
2020-04-04remove also files.netsmb from herejdolecek
2020-04-04remove SMBFS and nsmb(4) - kernel partjdolecek
it's unmaintained and supports only obsolete SMB1
2020-03-31dme needs miinisimura
2020-03-08undo previous since config has been fixedchristos
2020-03-07Fix MIPS builds by working around an apparent bug in config(8)'s elifthorpej
handling.
2020-03-05Also exclude EXEC_AOUT stuff for aarch64pgoyette
XXX Pullup-9 and -8
2020-03-05Fix comment - thanks Ryo Shimizupgoyette