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path: root/sys/dev/pci/if_wmreg.h
AgeCommit message (Expand)Author
2022-07-11Pull up the following revisions, requested by msaitoh in ticket #1477:martin
2021-11-20Pull up the following, requested by msaitoh in ticket #1373:martin
2020-09-23Pull up following revision(s) (requested by msaitoh in ticket #1093):martin
2020-07-10Pull up the following revisions, requested by msaitoh in ticket #994:martin
2020-01-26Pull up the following (via patch), requested by msaitoh in ticket #650:martin
2019-07-23 Define RETA_ENTRY_MASK_Q(used in RSS redirection table) correctly.msaitoh
2019-06-07 Use unsigned. Found by UBSan. OK'd by kamil.msaitoh
2019-02-28Typo (s/vaule/value/)khorben
2019-01-31Add some workarounds which use EMI register or EEE related:msaitoh
2018-12-20- Don't setup WoL on non-WoL capable port.msaitoh
2018-12-14- Fix availability detection of WoL on some chips. This change has no effectmsaitoh
2018-11-19- Control TX/RX descriptor snooping control bits on ICH8 and newer.msaitoh
2018-11-02 Add workaround for DMA hang problem which result in TX device timeout onmsaitoh
2018-04-12No binary change:msaitoh
2018-04-10 SW PHY Config Enable bit for ICH8 B0 stepping is not bit 1 but bit 0.msaitoh
2017-11-22 Revert if_wmreg.h 1.104 and if_wm.c 1.542. It's not required to mask othermsaitoh
2017-10-23fix wm(4) vlan panic. Reported and tested by Tom Ivar Helbekkmo, thanks.knakahara
2017-07-26- Our MII readreg/writereg API has not way to detect an error.msaitoh
2017-07-13- Call wm_kmrn_lock_loss_workaround_ich8lan() before any PHY access inmsaitoh
2017-07-12 Disable D0 LPLU on 8257[12356], 82580, I350 and I21[01], too. Before this co...msaitoh
2017-06-26- Make new wm_phy_post_reset() and use this function at all location aftermsaitoh
2017-06-26- Fix wm_set_ral():msaitoh
2017-02-28fix EITR setting.knakahara
2017-02-02Fix typo in comment.msaitoh
2017-02-01tabifyknakahara
2017-01-16support {extended, advanced} receive descriptor for wm(4).knakahara
2016-12-13- Change to use 2500Base-KX correctly on C2000(I354). It worked, but themsaitoh
2016-11-16 Sync wm_smbustopci() with Linux and FreeBSD. This change effects PCH andmsaitoh
2016-11-16Add three workarounds for PCH_{LPT,SPT}.msaitoh
2016-11-14Sort registers. No functional change.msaitoh
2016-11-11The MEHE bit in the CTRL register is not bit 17 but 19.msaitoh
2016-05-06Basic support for I219. It doesn't work on I219, so it's disabled.msaitoh
2015-12-25- Fix RAL table's size of PCH2 and PCH_LPT.msaitoh
2015-10-27 Move the definition of CTRL_EXT_PHYPDEN and use __BIT(). No binary change.msaitoh
2015-10-23 PHY_CTRL_GBE_DIS is not bit 4 but bit 6. This change has no any effect bymsaitoh
2015-10-13fix RXCSUM_CRCOFL bit of WMREG_RXCSUM register.knakahara
2015-10-13support RX multiqueue.knakahara
2015-10-13change const value register macros to macro expressions to support multiqueue.knakahara
2015-10-08- ACK Accelerate Disable in the RFCTL register is not bit 13 but 12.msaitoh
2015-09-30fix IVARs offset for 82580 and newer.knakahara
2015-09-30- Add workaround for 82574 Errata 25 and 82583 Errata 12 "Dropped RX packets"msaitoh
2015-09-07- Check iNVM's image version and print it.msaitoh
2015-06-13 Add MSI/MSI-X support written by Kengo Nakahara. Some old devices' supportmsaitoh
2015-06-06- Add workaround for I210 Errata 25 and I211 Errata 10.msaitoh
2015-06-06 Print NVM image version.msaitoh
2015-06-06 Revert previos. Sorry, I committed in another working directory...msaitoh
2015-06-06 Print NVM image version.msaitoh
2015-06-02Fix a lot of bugs to make 82575 and newer's SERDES based systems work.msaitoh
2015-05-22- Currently, WM_F_EEE bit is not set on all chips. it's intended to notmsaitoh
2015-05-16 Add support iNVM (integrated Non-Volatile Memory) for I21[01]. This changemsaitoh