| Age | Commit message (Collapse) | Author |
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by GCC for HPPA to hold the return address where the signal trampoline
will resume. XXX Same treatment is needed for HPPA64, but not done as
part of this commit.
Thanks to thorpej for help with this. (ages ago)
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by GCC for SuperH for GBR, MACH, MACL, and SR.
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by GCC for AArch64 to hold the return address where the signal trampoline
will resume.
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that GCC defines for the PC / return address. This is simply an alias for
the same internal PC register number.
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by GCC for PPC32 to hold the return address where the signal trampoline
will resume, as well as for the CTR and XER registers.
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by GCC for Alpha to hold the return address where the signal trampoline
will resume.
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by GCC for MIPS64 to hold the MDHI and MDLO registers, as well as the return
address where the signal trampoline will resume.
- In the MIPS64 validFloatVectorRegister(), compare against the internal
register numbers, not the DWARF register numbers.
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by GCC for MIPS to hold the MDHI and MDLO registers, as well as the return
address where the signal trampoline will resume. XXX Same treatment is
needed for MIPS64, but not done as part of this commit.
- In the MIPS validFloatVectorRegister(), compare against the internal
register numbers, not the DWARF register numbers.
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Stop using enum for flags, as per request from joerg.
#define constants and #undef after use.
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Bump LAST_REGISTER and LAST_RESTORE_REG to REGNO_ARM32_S31 for arm.
There are two numbering schemes for VFPv2 registers: s0-s31 and d0-d15.
The former is used by GCC, and the latter is by LLVM. Since libunwind was
derived from LLVM, it has never supported the former. This results in
crashes for GCC-compiled binaries in exception handler of C++, if it
encounters VFPv2 registers when unwinding frames.
This commit adds support for s0-s31 numbering to libunwind. I choose an
implementation in which VFPv2 registers are ``double-counted'' as s0-s31
AND d0-d15. This does not cause real problems, since the former is only
used by GCC, and the later is by LLVM. That is, different numbering
schemes cannot appear in a same frame. To make sure, assertions are added
in order to check this.
I've confirmed that no regression for ATF both for GCC- and LLVM-compiled
userlands.
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Fix logic error in copyFloatVectorRegister() for arm; copy s0-s31 or
d0-d31, not both.
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Fix pointer arithmetic when copying s0-s31 registers for arm.
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Fix DWARF/internal register numbers of s31 for arm.
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Fix for jumpto() armeb; use word-wise load for flags, instead of byte-wise one.
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copyFloatVectorRegister(): Assert register number is valid to make sure.
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Misc style fixes for clarity:
- Rename lazyVFP1() and lazyVFP3() to lazyVFPv2() and lazyVFPv3(),
respectively. Note that VFPv1 was obsoleted and replaced by VFPv2.
- Introduce enum for flags.
- Add few comments.
No functional changes.
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nesting issues between malloc and backtrace when using LSan.
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starting from returning the wrong value from the constructor to
completely bogus offset computations. Drop the ELR support for now.
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this is not the same as the internal encoding, since the Link Register
is deliberately non-continous from the other general purpose register
values. To handle this, always translate the value into the internal
format.
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and breaks exceptions.
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years. Adopt the new convention that it is call-site specific and that
it should be applied before moving the IP by personality routines, but
not during normal unwinding. Further discussion can be found in
LLVM's phabricator review D38680.
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halfs. Compensate.
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to the start of the range. PR 49444.
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evbarm64-el
This is clang only. While gcc4.8 supports aarch64, no netbsd support has
been written for aarch64 with gcc4.8.
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now.
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there could still be more -- i only looked for lines matching
both "HAVE_GCC" and "4" as words (grep -w.)
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instruction.
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Kledzik.
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