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path: root/usr.sbin/cpuctl
AgeCommit message (Expand)Author
2023-07-06Add Alder Lake-N.msaitoh
2023-07-05CPU model 0x5a is not Atom E3500 but Atom Z3500.msaitoh
2023-03-06Unless -v is given, ignore EEXIST errors from the IOC_CPU_UCODE_APPLY ioctl()kre
2023-02-14Add some CPUID bits from PPR for AMD Family 19h Model 61h Revision B1.msaitoh
2023-02-03MPIDR is 64bits. Without this AFF3 would always be zero.skrll
2022-12-30Add Raptor Lake and Sapphire Rapids.msaitoh
2022-12-30Print cpuid 7 sub-leaf 1 %ebx, %edx and sub-leaf 2 %edx.msaitoh
2022-11-17s/features 2/features2/msaitoh
2022-11-16s/Instruction-Based Sampling/IBS/msaitoh
2022-11-16Add CPUID Fn8000_0022 AMD Extended Performance Monitoring and Debug.msaitoh
2022-11-16Add CPUID Fn8000_0021 AMD Extended Features Identification 2.msaitoh
2022-11-16Print AMD RAS features and Instruction-Based Sampling features.msaitoh
2022-08-06s/blity/bility/ in various words, mainly in comments.andvar
2022-06-15Modify output of CPUID Fn0000000a.msaitoh
2022-04-30add CPU_ID_APPLE_M1_ICESTORM and CPU_ID_APPLE_M1_FIRESTORM.ryo
2022-02-01allow "cpuN" as well as "N" to specific a CPU.mrg
2022-01-29Decode Intel Hybrid Information Enumeration (CPUID Fn0000_001a).msaitoh
2022-01-27Remove debug code and simplify. No functional change.msaitoh
2022-01-13Add Alder Lake, Rocket Lake and Sapphire Rapids. From the latest Intel SDM.msaitoh
2022-01-06display the raw value of each field when -v specifiedryo
2022-01-06fix typoryo
2022-01-06Added more field definitions for ARMv8.x system registersryo
2022-01-06macroify. NFC.ryo
2022-01-05fix ID_AA64ISAR0_EL1.ATOMIC field definitionryo
2021-12-11remove clause 3 from all my licenses that aren't conflicting withmrg
2021-12-09Print 1GB TLB entry at the same leve's line.msaitoh
2021-12-05auxilary -> auxiliarymsaitoh
2021-10-27decode SMT parts for AMD family >= 0x17, not just 0x17.mrg
2021-10-07Move some common functions into x86/identcpu_subr.c. No functional change.msaitoh
2021-09-27Improve variable sized TLB's output.msaitoh
2021-09-27Add Load Only TLB and Store Only TLB.msaitoh
2021-09-27Fix a bug that some TLB related lines were not printed.msaitoh
2021-09-27Add ':' for readability.msaitoh
2021-07-12 Add 0x96(Elkhart Lake) and 0x9c(Jasper Lake).msaitoh
2021-07-100x6a and 0x6c are 3rd gen Xeon Scalable (Ice Lake).msaitoh
2021-05-17Teach cpuctl(8) about some additional aarch64 feature bits.riastradh
2021-01-16trailing whitespacejmcneill
2021-01-16ID_AA64PFR0_EL1.GIC=0 means that the CPU interface system registers arejmcneill
2021-01-04sync cpuids[] of sys/arch/aarch64/aarch64/cpu.c r1.43ryo
2020-11-24- Print CPUID 0x8000008 %ebx on Intel, too. Intel now supports WBNOINVD.msaitoh
2020-10-10Report half-precision FP and SIMD supportjmcneill
2020-09-05x86: fix several CPUID flagsmaxv
2020-07-05(cpuctl/aarch64) Add some more aa64isar0_eli1 flags.riastradh
2020-07-01show clidr_el1 and ctr_el0.ryo
2020-06-01 Add 0xa5 and 0xa6 for Comet Lake.msaitoh
2020-05-10Teach cpuctl(8) about ARMv8.5-RNG RNDR/RNDRRS support.riastradh
2020-04-21Get TSC frequency from CPUID 0x15 and/or x16 for newer Intel processors.msaitoh
2020-04-16No functional change:msaitoh
2020-04-06 Print CPUID 0x80000007 %edx on both Intel and AMD.msaitoh
2020-04-06 Remove ci_max_ext_cpuid because it's the same as ci_cpuid_extlevel.msaitoh