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authorchristos <christos@NetBSD.org>2016-01-29 14:42:43 +0000
committerchristos <christos@NetBSD.org>2016-01-29 14:42:43 +0000
commit438aacb6af3817652f0d4e33aa4acaaedee296c0 (patch)
tree56f5ac01227a3940421e6d2a37abbfbfc8c20bf3 /external/gpl3/binutils/dist/include/opcode
parent82d15a20f882d216ef425fc25bff8d953e3e9fc8 (diff)
merge conflicts, regen for x86.
Diffstat (limited to 'external/gpl3/binutils/dist/include/opcode')
-rw-r--r--external/gpl3/binutils/dist/include/opcode/ChangeLog901
-rw-r--r--external/gpl3/binutils/dist/include/opcode/hppa.h12
-rw-r--r--external/gpl3/binutils/dist/include/opcode/mips.h1062
-rw-r--r--external/gpl3/binutils/dist/include/opcode/or32.h181
-rw-r--r--external/gpl3/binutils/dist/include/opcode/ppc.h41
5 files changed, 1653 insertions, 544 deletions
diff --git a/external/gpl3/binutils/dist/include/opcode/ChangeLog b/external/gpl3/binutils/dist/include/opcode/ChangeLog
index cb9f60f335f..0aee1949909 100644
--- a/external/gpl3/binutils/dist/include/opcode/ChangeLog
+++ b/external/gpl3/binutils/dist/include/opcode/ChangeLog
@@ -1,40 +1,825 @@
-2013-02-12 Yufeng Zhang <yufeng.zhang@arm.com>
+2015-12-15 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (enum aarch64_opnd_qualifier): Add
+ AARCH64_OPND_QLF_V_2H.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (aarch64_opnd): Add AARCH64_OPND_BARRIER_PSB.
+ * aarch64-asm-2.c: Regenerate.
+ * aarch64-dis-2.c: Regenerate.
+ * aarch64-opc-2.c: Regenerate.
+ * aarch64-opc.c (aarch64_hint_options): Add "csync".
+ (aarch64_print_operands): Handle AARCH64_OPND_BARRIER_PSB.
+ * aarch64-tbl.h (aarch64_feature_stat_profile): New.
+ (STAT_PROFILE): New.
+ (aarch64_opcode_table): Add "psb".
+ (AARCH64_OPERANDS): Add "BARRIER_PSB".
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (aarch64_hint_options): Declare.
+ (aarch64_opnd_info): Add field hint_option.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_PROFILE): New.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (aarch64_sys_ins_reg_supported_p): Declare.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (aarch64_sys_ins_reg): Replace has_xt with flags.
+ (aarch64_sys_ins_reg_has_xt): Declare.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_RAS): New.
+ (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_RAS.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_F16): Fix clash with
+ AARCH64_FEATURE_V8_1.
+ (AARCH64_ARCH_V8_1): Add AARCH64_FEATURE_CRC.
+ (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_CRC and
+ AARCH64_FEATURE_V8_1.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_F16): New.
+ (AARCH64_ARCH_V8_2): Add AARCH64_FEATURE_F16 to ARMv8.2
+ features.
+
+2015-12-14 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (aarch64_op): Add OP_BFC.
+
+2015-12-09 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_V8_2): New.
+ (AARCH64_ARCH_V8_2): New.
+
+2015-12-08 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_V8_1): New.
+ (AARCH64_ARCH_v8_1): Add AARCH64_FEATURE_V8_1.
+
+2015-11-11 Alan Modra <amodra@gmail.com>
+ Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_POWER9): New define.
+ (PPC_OPCODE_VSX3): Likewise.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx.h (enum RX_Opcode_ID): Add more NOP opcodes.
+
+2015-11-02 Nick Clifton <nickc@redhat.com>
+
+ * rx.h (enum RX_Operand_Type): Add RX_Operand_Zero_Indirect.
+
+2015-10-28 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64.h (aarch64_decode_insn): Update declaration.
+
+2015-10-07 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64.h (aarch64_sys_ins_reg) <template>: Removed.
+ <name>: New field.
+
+2015-10-07 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64.h [__cplusplus]: Wrap in extern "C".
+
+2015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
+ Cupertino Miranda <cmiranda@synopsys.com>
+
+ * arc-func.h: New file.
+ * arc.h: Likewise.
+
+2015-10-02 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64.h (aarch64_zero_register_p): Move the declaration
+ to column one.
+
+2015-10-02 Yao Qi <yao.qi@linaro.org>
+
+ * aarch64.h (aarch64_decode_insn): Declare it.
+
+2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
+
+ * s390.h (S390_INSTR_FLAG_HTM): New flag.
+ (S390_INSTR_FLAG_VX): New flag.
+ (S390_INSTR_FLAG_FACILITY_MASK): New flag mask.
+
+2015-09-23 Nick Clifton <nickc@redhat.com>
+
+ * ppc.h (PPC_OPSHIFT_INV): Use an unsigned constant when left
+ shifting.
+
+2015-09-22 Nick Clifton <nickc@redhat.com>
+
+ * rx.h (enum RX_Size): Add RX_Bad_Size entry.
+
+2015-09-09 Daniel Santos <daniel.santos@pobox.com>
+
+ * visium.h (gen_reg_table): Make static.
+ (fp_reg_table): Likewise.
+ (cc_table): Likewise.
+
+2015-07-20 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm.h (ARM_AEXT_V6ZK): Rename to ARM_AEXT_V6KZ.
+ (ARM_AEXT_V6ZKT2): Rename to ARM_AEXT_V6KZT2.
+ (ARM_ARCH_V6ZK): Rename to ARM_ARCH_V6KZ.
+ (ARM_ARCH_V6ZKT2): Rename to ARM_ARCH_V6KZT2.
+
+2015-07-03 Alan Modra <amodra@gmail.com>
+
+ * ppc.h (PPC_OPCODE_750, PPC_OPCODE_7450, PPC_OPCODE_860): Define.
+
+2015-07-01 Sandra Loosemore <sandra@codesourcery.com>
+ Cesar Philippidis <cesar@codesourcery.com>
+
+ * nios2.h (enum iw_format_type): Add R2 formats.
+ (enum overflow_type): Add signed_immed12_overflow and
+ enumeration_overflow for R2.
+ (struct nios2_opcode): Document new argument letters for R2.
+ (REG_3BIT, REG_LDWM, REG_POP): Define.
+ (includes): Include nios2r2.h.
+ (nios2_r2_opcodes, nios2_num_r2_opcodes): Declare.
+ (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): Declare.
+ (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): Declare.
+ (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): Declare.
+ (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): Declare.
+ (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings):
+ Declare.
+ * nios2r2.h: New file.
+
+2015-06-19 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPERAND_OPTIONAL_VALUE): New.
+ (ppc_optional_operand_value): New inline function.
+
+2015-06-04 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_V8_1): New.
+
+2015-06-03 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm.h (FPU_ARCH_CRYPTO_NEON_VFP_ARMV8_1): New.
+ (ARM_ARCH_V8_1A): New.
+ (ARM_ARCH_V8_1A_FP): New.
+ (ARM_ARCH_V8_1A_SIMD): New.
+ (ARM_ARCH_V8_1A_CRYPTOV1): New.
+ (ARM_FEATURE_CORE): New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm.h (ARM_EXT2_PAN): New.
+ (ARM_FEATURE_CORE_HIGH): New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * arm.h (ARM_FEATURE_ALL): New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_RDMA): New.
+
+2015-06-02 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_LOR): New.
+
+2015-06-01 Matthew Wahab <matthew.wahab@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_PAN): New.
+ (aarch64_sys_reg_supported_p): Declare.
+ (aarch64_pstatefield_supported_p): Declare.
+
+2015-04-30 DJ Delorie <dj@redhat.com>
+
+ * rl78.h (RL78_Dis_Isa): New.
+ (rl78_decode_opcode): Add ISA parameter.
+
+2015-03-24 Terry Guo <terry.guo@arm.com>
+
+ * arm.h (arm_feature_set): Extended to provide more available bits.
+ (ARM_ANY): Updated to follow above new definition.
+ (ARM_CPU_HAS_FEATURE): Likewise.
+ (ARM_CPU_IS_ANY): Likewise.
+ (ARM_MERGE_FEATURE_SETS): Likewise.
+ (ARM_CLEAR_FEATURE): Likewise.
+ (ARM_FEATURE): Likewise.
+ (ARM_FEATURE_COPY): New macro.
+ (ARM_FEATURE_EQUAL): Likewise.
+ (ARM_FEATURE_ZERO): Likewise.
+ (ARM_FEATURE_CORE_EQUAL): Likewise.
+ (ARM_FEATURE_LOW): Likewise.
+ (ARM_FEATURE_CORE_LOW): Likewise.
+ (ARM_FEATURE_CORE_COPROC): Likewise.
+
+2015-02-19 Pedro Alves <palves@redhat.com>
+
+ * cgen.h [__cplusplus]: Wrap in extern "C".
+ * msp430-decode.h [__cplusplus]: Likewise.
+ * nios2.h [__cplusplus]: Likewise.
+ * rl78.h [__cplusplus]: Likewise.
+ * rx.h [__cplusplus]: Likewise.
+ * tilegx.h [__cplusplus]: Likewise.
+
+2015-01-28 James Bowman <james.bowman@ftdichip.com>
+
+ * ft32.h: New file.
+
+2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
+
+ * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_Z13.
+
+2015-01-01 Alan Modra <amodra@gmail.com>
+
+ Update year range in copyright notice of all files.
+
+2014-12-27 Anthony Green <green@moxielogic.com>
+
+ * moxie.h (MOXIE_F1_AiB2, MOXIE_F1_ABi2): Renamed from
+ MOXIE_F1_AiB4 and MOXIE_F1_ABi2.
+
+2014-12-06 Eric Botcazou <ebotcazou@adacore.com>
+
+ * visium.h: New file.
+
+2014-11-28 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2.h (NIOS2_INSN_ADDI, NIOS2_INSN_ANDI): Delete.
+ (NIOS2_INSN_ORI, NIOS2_INSN_XORI): Delete.
+ (NIOS2_INSN_OPTARG): Renumber.
+
+2014-11-06 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2.h (nios2_find_opcode_hash): Add mach parameter to
+ declaration. Fix obsolete comment.
+
+2014-10-23 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2.h (enum iw_format_type): New.
+ (struct nios2_opcode): Update comments. Add size and format fields.
+ (NIOS2_INSN_OPTARG): New.
+ (REG_NORMAL, REG_CONTROL, REG_COPROCESSOR): New.
+ (struct nios2_reg): Add regtype field.
+ (GET_INSN_FIELD, SET_INSN_FIELD): Delete.
+ (IW_A_LSB, IW_A_MSB, IW_A_SZ, IW_A_MASK): Delete.
+ (IW_B_LSB, IW_B_MSB, IW_B_SZ, IW_B_MASK): Delete.
+ (IW_C_LSB, IW_C_MSB, IW_C_SZ, IW_C_MASK): Delete.
+ (IW_IMM16_LSB, IW_IMM16_MSB, IW_IMM16_SZ, IW_IMM16_MASK): Delete.
+ (IW_IMM26_LSB, IW_IMM26_MSB, IW_IMM26_SZ, IW_IMM26_MASK): Delete.
+ (IW_OP_LSB, IW_OP_MSB, IW_OP_SZ, IW_OP_MASK): Delete.
+ (IW_OPX_LSB, IW_OPX_MSB, IW_OPX_SZ, IW_OPX_MASK): Delete.
+ (IW_SHIFT_IMM5_LSB, IW_SHIFT_IMM5_MSB): Delete.
+ (IW_SHIFT_IMM5_SZ, IW_SHIFT_IMM5_MASK): Delete.
+ (IW_CONTROL_REGNUM_LSB, IW_CONTROL_REGNUM_MSB): Delete.
+ (IW_CONTROL_REGNUM_SZ, IW_CONTROL_REGNUM_MASK): Delete.
+ (OP_MASK_OP, OP_SH_OP): Delete.
+ (OP_MASK_IOP, OP_SH_IOP): Delete.
+ (OP_MASK_IRD, OP_SH_IRD): Delete.
+ (OP_MASK_IRT, OP_SH_IRT): Delete.
+ (OP_MASK_IRS, OP_SH_IRS): Delete.
+ (OP_MASK_ROP, OP_SH_ROP): Delete.
+ (OP_MASK_RRD, OP_SH_RRD): Delete.
+ (OP_MASK_RRT, OP_SH_RRT): Delete.
+ (OP_MASK_RRS, OP_SH_RRS): Delete.
+ (OP_MASK_JOP, OP_SH_JOP): Delete.
+ (OP_MASK_IMM26, OP_SH_IMM26): Delete.
+ (OP_MASK_RCTL, OP_SH_RCTL): Delete.
+ (OP_MASK_IMM5, OP_SH_IMM5): Delete.
+ (OP_MASK_CACHE_OPX, OP_SH_CACHE_OPX): Delete.
+ (OP_MASK_CACHE_RRS, OP_SH_CACHE_RRS): Delete.
+ (OP_MASK_CUSTOM_A, OP_SH_CUSTOM_A): Delete.
+ (OP_MASK_CUSTOM_B, OP_SH_CUSTOM_B): Delete.
+ (OP_MASK_CUSTOM_C, OP_SH_CUSTOM_C): Delete.
+ (OP_MASK_CUSTOM_N, OP_SH_CUSTOM_N): Delete.
+ (OP_<insn>, OPX_<insn>, OP_MATCH_<insn>, OPX_MATCH_<insn>): Delete.
+ (OP_MASK_<insn>, OP_MASK): Delete.
+ (GET_IW_A, GET_IW_B, GET_IW_C, GET_IW_CONTROL_REGNUM): Delete.
+ (GET_IW_IMM16, GET_IW_IMM26, GET_IW_OP, GET_IW_OPX): Delete.
+ Include nios2r1.h to define new instruction opcode constants
+ and accessors.
+ (nios2_builtin_opcodes): Rename to nios2_r1_opcodes.
+ (bfd_nios2_num_builtin_opcodes): Rename to nios2_num_r1_opcodes.
+ (bfd_nios2_num_opcodes): Rename to nios2_num_opcodes.
+ (NUMOPCODES, NUMREGISTERS): Delete.
+ * nios2r1.h: New file.
+
+2014-10-17 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc.h (HWCAP2_VIS3B): Documentation improved.
+
+2014-10-09 Jose E. Marchesi <jose.marchesi@oracle.com>
+
+ * sparc.h (sparc_opcode): new field `hwcaps2'.
+ (HWCAP2_FJATHPLUS): New define.
+ (HWCAP2_VIS3B): Likewise.
+ (HWCAP2_ADP): Likewise.
+ (HWCAP2_SPARC5): Likewise.
+ (HWCAP2_MWAIT): Likewise.
+ (HWCAP2_XMPMUL): Likewise.
+ (HWCAP2_XMONT): Likewise.
+ (HWCAP2_NSEC): Likewise.
+ (HWCAP2_FJATHHPC): Likewise.
+ (HWCAP2_FJDES): Likewise.
+ (HWCAP2_FJAES): Likewise.
+ Document the new operand kind `{', corresponding to the mcdper
+ ancillary state register.
+ Document the new operand kind }, which represents frsd floating
+ point registers (double precision) which must be the same than
+ frs1 in its containing instruction.
+
+2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+
+ * nds32.h: Add new opcode declaration.
+
+2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
+ Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * mips.h (mips_operand_type): Add new entries: OP_SAME_RS_RT,
+ OP_CHECK_PREV and OP_NON_ZERO_REG. Add descriptions for the MIPS R6
+ instruction arguments: -a, -b, -d, -s, -t, -u, -v, -w, -x, -y, -A, -B,
+ +I, +O, +R, +:, +\, +", +;
+ (mips_check_prev_operand): New struct.
+ (INSN2_FORBIDDEN_SLOT): New define.
+ (INSN_ISA32R6): New define.
+ (INSN_ISA64R6): New define.
+ (INSN_UPTO32R6): New define.
+ (INSN_UPTO64R6): New define.
+ (mips_isa_table): Add INSN_UPTO32R6 and INSN_UPTO64R6.
+ (ISA_MIPS32R6): New define.
+ (ISA_MIPS64R6): New define.
+ (CPU_MIPS32R6): New define.
+ (CPU_MIPS64R6): New define.
+ (cpu_is_member): Add cases for CPU_MIPS32R6, and CPU_MIPS64R6.
+
+2014-09-03 Jiong Wang <jiong.wang@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_LSE): New feature added.
+ (aarch64_opnd): Add AARCH64_OPND_PAIRREG.
+ (aarch64_insn_class): Add lse_atomic.
+ (F_LSE_SZ): New field added.
+ (opcode_has_special_coder): Recognize F_LSE_SZ.
+
+2014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Document the move of `MICROMIPSOP_*_CODE10' from `B'
+ over to `+J'.
+
+2014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
+
+ * mips.h (INSN_LOAD_COPROC_DELAY): Rename to...
+ (INSN_LOAD_COPROC): New define.
+ (INSN_COPROC_MOVE_DELAY): Rename to...
+ (INSN_COPROC_MOVE): New define.
+
+2014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
+ Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
+ Pitchumani Sivanupandi <pitchumani.s@atmel.com>
+ Soundararajan <Sounderarajan.D@atmel.com>
+
+ * avr.h (AVR_ISA_TINY): Define avrtiny specific ISA.
+ (AVR_ISA_2xxxa): Define ISA without LPM.
+ (AVR_ISA_AVRTINY): Define avrtiny arch ISA.
+ Add doc for contraint used in 16 bit lds/sts.
+ Adjust ISA group for icall, ijmp, pop and push.
+ Add 16 bit lds/sts encoding and update 32 bit lds/sts constraints.
+
+2014-05-19 Nick Clifton <nickc@redhat.com>
+
+ * msp430.h (struct msp430_operand_s): Add vshift field.
+
+2014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips.h (INSN_ISA_MASK): Updated.
+ (INSN_ISA32R3): New define.
+ (INSN_ISA32R5): New define.
+ (INSN_ISA64R3): New define.
+ (INSN_ISA64R5): New define.
+ (INSN_ISA64, INSN_ISA64R2, INSN_ISA3_32, INSN_ISA3_32R2, INSN_ISA4_32
+ INSN_ISA4_32R2, INSN_ISA5_32R2): Renumbered.
+ (mips_isa_table): Add entries for mips32r3, mips32r5, mips64r3 and
+ mips64r5.
+ (INSN_UPTO32R3): New define.
+ (INSN_UPTO32R5): New define.
+ (INSN_UPTO64R3): New define.
+ (INSN_UPTO64R5): New define.
+ (ISA_MIPS32R3): New define.
+ (ISA_MIPS32R5): New define.
+ (ISA_MIPS64R3): New define.
+ (ISA_MIPS64R5): New define.
+ (CPU_MIPS32R3): New define.
+ (CPU_MIPS32R5): New define.
+ (CPU_MIPS64R3): New define.
+ (CPU_MIPS64R5): New define.
+
+2014-05-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (mips_isa_table): Avoid hard-coding INSN_ISA* values.
+
+2014-04-22 Christian Svensson <blue@cmd.nu>
+
+ * or32.h: Delete.
+
+2014-03-05 Alan Modra <amodra@gmail.com>
+
+ Update copyright years.
+
+2013-12-16 Andrew Bennett <andrew.bennett@imgtec.com>
+
+ * mips.h: Updated description of +o, +u, +v and +w for MIPS and
+ microMIPS.
+
+2013-12-13 Kuan-Lin Chen <kuanlinchentw@gmail.com>
+ Wei-Cheng Wang <cole945@gmail.com>
+
+ * nds32.h: New file for Andes NDS32.
+
+2013-12-07 Mike Frysinger <vapier@gentoo.org>
+
+ * bfin.h: Remove +x file mode.
+
+2013-11-20 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_pstatefields): Change element type to
+ aarch64_sys_reg.
+
+2013-11-18 Renlin Li <Renlin.Li@arm.com>
+
+ * arm.h (ARM_AEXT_V7VE): New define.
+ (ARM_ARCH_V7VE): New define.
+ (ARM_ARCH_V7A_IDIV_MP_SEC_VIRT): Removed.
+
+2013-11-18 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ Revert
+
+ 2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
+ (aarch64_sys_reg_writeonly_p): Ditto.
+
+2013-11-15 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_sys_reg_readonly_p): New declaration.
+ (aarch64_sys_reg_writeonly_p): Ditto.
+
+2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_sys_reg): New typedef.
+ (aarch64_sys_regs): Change to define with the new type.
+ (aarch64_sys_reg_deprecated_p): Declare.
+
+2013-11-05 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (enum aarch64_operand_class): Add AARCH64_OPND_CLASS_COND.
+ (enum aarch64_opnd): Add AARCH64_OPND_COND1.
+
+2013-10-14 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
+
+ * mips.h (mips_operand_type): Add OP_IMM_INDEX and OP_REG_INDEX.
+ (mips_reg_operand_type): Add OP_REG_MSA and OP_REG_MSA_CTRL.
+ For MIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+ +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+ For MIPS, update extension character sequences after +.
+ (ASE_MSA): New define.
+ (ASE_MSA64): New define.
+ For microMIPS, add comments for +d, +e, +h, +k, +l, +n, +o, +u, +v, +w,
+ +x, +T, +U, +V, +W, +~, +!, +@, +#, +$, +%, +^, +&, +*, +|.
+ For microMIPS, update extension character sequences after +.
+
+2013-08-23 Yuri Chornoivan <yurchor@ukr.net>
+
+ PR binutils/15834
+ * i960.h: Fix typos.
+
+2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Remove references to "+I" and imm2_expr.
+
+2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (M_DEXT, M_DINS): Delete.
+
+2013-08-19 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (OP_OPTIONAL_REG): New mips_operand_type.
+ (mips_optional_operand_p): New function.
+
+2013-08-04 Jürgen Urban <JuergenUrban@gmx.de>
+ Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Document new VU0 operand characters.
+ (OP_VU0_SUFFIX, OP_VU0_MATCH_SUFFIX): New mips_operand_types.
+ (OP_REG_VF, OP_REG_VI, OP_REG_R5900_I, OP_REG_R5900_Q, OP_REG_R5900_R)
+ (OP_REG_R5900_ACC): New mips_reg_operand_types.
+ (INSN2_VU0_CHANNEL_SUFFIX): New macro.
+ (mips_vu0_channel_mask): Declare.
+
+2013-08-03 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (mips_pcrel_operand): Inherit from mips_int_operand.
+ (mips_int_operand_min, mips_int_operand_max): New functions.
+ (mips_decode_pcrel_operand): Use mips_decode_int_operand.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (mips_decode_reg_operand): New function.
+ (INSN_WRITE_SHIFT, INSN_WRITE_1, INSN_WRITE_2, INSN_WRITE_ALL)
+ (INSN_READ_SHIFT, INSN_READ_1, INSN_READ_2, INSN_READ_3, INSN_READ_4)
+ (INSN_READ_ALL, INSN_READ_GPR_24, INSN_WRITE_GPR_24, INSN_UDI):
+ New macros.
+ (INSN_WRITE_GPR_D, INSN_WRITE_GPR_T, INSN_WRITE_FPR_D)
+ (INSN_WRITE_FPR_S, INSN_WRITE_FPR_T, INSN_READ_GPR_S, INSN_READ_GPR_T)
+ (INSN_READ_FPR_S, INSN_READ_FPR_T, INSN_READ_FPR_R, INSN_WRITE_GPR_S)
+ (INSN2_WRITE_GPR_Z, INSN2_WRITE_FPR_Z, INSN2_READ_GPR_Z)
+ (INSN2_READ_FPR_Z, INSN2_READ_GPR_D, INSN2_READ_FPR_D)
+ (INSN2_WRITE_GPR_MB, INSN2_READ_GPR_MC, INSN2_MOD_GPR_MD)
+ (INSN2_READ_GPR_ME, INSN2_MOD_GPR_MF, INSN2_READ_GPR_MG)
+ (INSN2_READ_GPR_MJ, INSN2_WRITE_GPR_MJ, INSN2_READ_GPR_MP)
+ (INSN2_WRITE_GPR_MP, INSN2_READ_GPR_MQ, INSN2_READ_GP)
+ (INSN2_WRITE_GPR_MH, INSN2_READ_GPR_MMN): Delete. Renumber other
+ macros to cover the gaps.
+ (INSN2_MOD_SP): Replace with...
+ (INSN2_WRITE_SP, INSN2_READ_SP): ...these new macros.
+ (MIPS16_INSN_WRITE_X, MIPS16_INSN_WRITE_Y, MIPS16_INSN_WRITE_Z)
+ (MIPS16_INSN_WRITE_T, MIPS16_INSN_WRITE_31, MIPS16_INSN_WRITE_GPR_Y)
+ (MIPS16_INSN_READ_X, MIPS16_INSN_READ_Y, MIPS16_INSN_READ_Z)
+ (MIPS16_INSN_READ_T, MIPS16_INSN_READ_SP, MIPS16_INSN_READ_GPR_X):
+ Delete.
+
+2013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
+ (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
+ (MIPS16_INSN_COND_BRANCH): Delete.
+
+2013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
+ Kirill Yukhin <kirill.yukhin@intel.com>
+ Michael Zolotukhin <michael.v.zolotukhin@intel.com>
+
+ * i386.h (BND_PREFIX_OPCODE): New.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (mips_operand_type): Add OP_ENTRY_EXIT_LIST and
+ OP_SAVE_RESTORE_LIST.
+ (decode_mips16_operand): Declare.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (mips_operand_type, mips_reg_operand_type): New enums.
+ (mips_operand, mips_int_operand, mips_mapped_int_operand)
+ (mips_msb_operand, mips_reg_operand, mips_reg_pair_operand)
+ (mips_pcrel_operand): New structures.
+ (mips_insert_operand, mips_extract_operand, mips_signed_operand)
+ (mips_decode_int_operand, mips_decode_pcrel_operand): New functions.
+ (decode_mips_operand, decode_micromips_operand): Declare.
+
+2013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Document MIPS16 "I" opcode.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h (M_ACLR_OB, M_ASET_OB, M_CACHE_OB, M_CACHEE_OB, M_L_DOB)
+ (M_LB_A, M_LBE_OB, M_LBU_A, M_LBUE_OB, M_LD_A, M_LD_OB, M_LDC2_OB)
+ (M_LDL_OB, M_LDM_OB, M_LDP_OB, M_LDR_OB, M_LH_A, M_LHE_OB, M_LHU_A)
+ (M_LHUE_OB, M_LL_OB, M_LLD_OB, M_LLE_OB, M_LS_A, M_LW_A, M_LWE_OB)
+ (M_LWC0_A, M_LWC1_A, M_LWC2_A, M_LWC2_OB, M_LWC3_A, M_LWL_A, M_LWL_OB)
+ (M_LWLE_OB, M_LWM_OB, M_LWP_OB, M_LWR_A, M_LWR_OB, M_LWRE_OB, M_LWU_OB)
+ (M_PREF_OB, M_PREFE_OB, M_S_DOB, M_SAA_OB, M_SAAD_OB, M_SC_OB)
+ (M_SCD_OB, M_SCE_OB, M_SD_A, M_SD_OB, M_SDC2_OB, M_SDL_OB, M_SDM_OB)
+ (M_SDP_OB, M_SDR_OB, M_SB_A, M_SBE_OB, M_SH_A, M_SHE_OB, M_SW_A)
+ (M_SWE_OB, M_SWC0_A, M_SWC1_A, M_SWC2_A, M_SWC2_OB, M_SWC3_A, M_SWL_A)
+ (M_SWL_OB, M_SWLE_OB, M_SWM_OB, M_SWP_OB, M_SWR_A, M_SWR_OB, M_SWRE_OB)
+ (M_ULD, M_ULH, M_ULHU, M_ULW, M_USH, M_USW, M_USD): Delete.
+ (M_ULD_A, M_ULH_A, M_ULHU_A, M_ULW_A, M_USH_A, M_USW_A, M_USD_A):
+ Rename to...
+ (M_ULD_AB, M_ULH_AB, M_ULHU_AB, M_ULW_AB, M_USH_AB, M_USW_AB)
+ (M_USD_AB): ...these.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Remove documentation of "[" and "]". Update documentation
+ of "k" and the MDMX formats.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Update documentation of "+s" and "+S".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Document "+i".
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Remove "mi" documentation. Update "mh" documentation.
+ (OP_MASK_MI, OP_SH_MI, MICROMIPSOP_MASK_MI, MICROMIPSOP_MASK_MI):
+ Delete.
+ (INSN2_WRITE_GPR_MHI): Rename to...
+ (INSN2_WRITE_GPR_MH): ...this.
+
+2013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Remove documentation of "+D" and "+T".
+
+2013-06-26 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
+ Use "source" rather than "destination" for microMIPS "G".
+
+2013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum
+ values.
+
+2013-06-23 Richard Sandiford <rdsandiford@googlemail.com>
+
+ * mips.h: Fix comment typo: "G" is _RS rather than _RD for microMIPS.
+
+2013-06-17 Catherine Moore <clm@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
+ Chao-Ying Fu <fu@mips.com>
+
+ * mips.h (OP_SH_EVAOFFSET): Define.
+ (OP_MASK_EVAOFFSET): Define.
+ (INSN_ASE_MASK): Delete.
+ (ASE_EVA): Define.
+ (M_CACHEE_AB, M_CACHEE_OB): New.
+ (M_LBE_OB, M_LBE_AB): New.
+ (M_LBUE_OB, M_LBUE_AB): New.
+ (M_LHE_OB, M_LHE_AB): New.
+ (M_LHUE_OB, M_LHUE_AB): New.
+ (M_LLE_AB, M_LLE_OB): New.
+ (M_LWE_OB, M_LWE_AB): New.
+ (M_LWLE_AB, M_LWLE_OB): New.
+ (M_LWRE_AB, M_LWRE_OB): New.
+ (M_PREFE_AB, M_PREFE_OB): New.
+ (M_SCE_AB, M_SCE_OB): New.
+ (M_SBE_OB, M_SBE_AB): New.
+ (M_SHE_OB, M_SHE_AB): New.
+ (M_SWE_OB, M_SWE_AB): New.
+ (M_SWLE_AB, M_SWLE_OB): New.
+ (M_SWRE_AB, M_SWRE_OB): New.
+ (MICROMIPSOP_SH_EVAOFFSET): Define.
+ (MICROMIPSOP_MASK_EVAOFFSET): Define.
+
+2013-06-12 Sandra Loosemore <sandra@codesourcery.com>
+
+ * nios2.h (OP_MATCH_ERET): Correct eret encoding.
+
+2013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
+
+ * mips.h (M_LQC2_AB, M_SQC2_AB): New macros.
+
+2013-05-09 Andrew Pinski <apinski@cavium.com>
+
+ * mips.h (OP_MASK_CODE10): Correct definition.
+ (OP_SH_CODE10): Likewise.
+ Add a comment that "+J" is used now for OP_*CODE10.
+ (INSN_ASE_MASK): Update.
+ (INSN_VIRT): New macro.
+ (INSN_VIRT64): New macro
+
+2013-05-02 Nick Clifton <nickc@redhat.com>
+
+ * msp430.h: Add patterns for MSP430X instructions.
+
+2013-04-06 David S. Miller <davem@davemloft.net>
+
+ * sparc.h (F_PREFERRED): Define.
+ (F_PREF_ALIAS): Define.
+
+2013-04-03 Nick Clifton <nickc@redhat.com>
+
+ * v850.h (V850_INVERSE_PCREL): Define.
+
+2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
+
+ PR binutils/15068
+ * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
+
+2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
+
+ PR binutils/15068
+ * tic6xc-insn-formats.h (FLD): Add use of bitfield array.
+ Add 16-bit opcodes.
+ * tic6xc-opcode-table.h: Add 16-bit insns.
+ * tic6x.h: Add support for 16-bit insns.
+
+2013-03-21 Michael Schewe <michael.schewe@gmx.net>
+
+ * h8300.h: Add MEMRELAX flag for mov.b/w/l @(d:32,ERs),Rd
+ and mov.b/w/l Rs,@(d:32,ERd).
+
+2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
+
+ PR gas/15082
+ * tic6x-opcode-table.h: Rename mpydp's specific operand type macro
+ from ORREGD1324 to ORXREGD1324 and make it cross-path-able through
+ tic6x_operand_xregpair operand coding type.
+ Make mpydp instruction cross-path-able, ie: remove the FIXed 'x'
+ opcode field, usu ORXREGD1324 for the src2 operand and remove the
+ TIC6X_FLAG_NO_CROSS.
+
+2013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
+
+ PR gas/15095
+ * tic6x.h (enum tic6x_coding_method): Add
+ tic6x_coding_dreg_(msb|lsb) field coding type in order to encode
+ separately the msb and lsb of a register pair. This is needed to
+ encode the opcodes in the same way as TI assembler does.
+ * tic6x-opcode-table.h: Modify absdp, dpint, dpsp, dptrunc, rcpdp
+ and rsqrdp opcodes to use the new field coding types.
+
+2013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
+
+ * arm.h (CRC_EXT_ARMV8): New constant.
+ (ARCH_CRC_ARMV8): New macro.
+
+2013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (AARCH64_FEATURE_CRC): New macro.
+
+2013-02-06 Sandra Loosemore <sandra@codesourcery.com>
+ Andrew Jenner <andrew@codesourcery.com>
+
+ Based on patches from Altera Corporation.
+
+ * nios2.h: New file.
+
+2013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
* aarch64.h (aarch64_op): Add OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2.
-2013-01-22 Alan Modra <amodra@gmail.com>
+2013-01-28 Alexis Deruelle <alexis.deruelle@gmail.com>
+
+ PR gas/15069
+ * tic6x-opcode-table.h: Fix encoding of BNOP instruction.
+
+2013-01-24 Nick Clifton <nickc@redhat.com>
+
+ * v850.h: Add e3v5 support.
+
+2013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h (aarch64_op): Remove OP_V_MOVI_B.
+
+2013-01-10 Peter Bergner <bergner@vnet.ibm.com>
+
+ * ppc.h (PPC_OPCODE_POWER8): New define.
+ (PPC_OPCODE_HTM): Likewise.
+
+2013-01-10 Will Newton <will.newton@imgtec.com>
+
+ * metag.h: New file.
+
+2013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
+
+ * cr16.h (make_instruction): Rename to cr16_make_instruction.
+ (match_opcode): Rename to cr16_match_opcode.
+
+2013-01-04 Juergen Urban <JuergenUrban@gmx.de>
+
+ * mips.h: Add support for r5900 instructions including lq and sq.
+
+2013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
+
+ * cr16.h (dwordU,wordU): Moved typedefs from cr16-dis.c
+ (make_instruction,match_opcode): Added function prototypes.
+ (cr16_words,cr16_allWords,cr16_currInsn): Declare as extern.
+
+2012-11-23 Alan Modra <amodra@gmail.com>
- Apply mainline patches
- 2012-11-23 Alan Modra <amodra@gmail.com>
* ppc.h (ppc_parse_cpu): Update prototype.
-2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
- Maciej W. Rozycki <macro@codesourcery.com>
+2012-10-14 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
- * mips.h (mips_opcode): Add the exclusions field.
- (OPCODE_IS_MEMBER): Remove macro.
- (cpu_is_member): New inline function.
- (opcode_is_member): Likewise.
+ * hppa.h (pa_opcodes): Use "cX" completer instead of "cx" in fstqx
+ opcodes. Likewise, use "cM" instead of "cm" in fstqs opcodes.
-2012-07-31 Chao-Ying Fu <fu@mips.com>
- Catherine Moore <clm@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
+2012-10-04 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
- * mips.h: Document microMIPS DSP ASE usage.
- (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
- microMIPS DSP ASE support.
- (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
- (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
- (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
- (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
- (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
- (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
- (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
+ * s390.h (s390_opcode_cpu_val): Add S390_OPCODE_ZEC12.
2012-09-04 Sergey A. Guriev <sergey.a.guriev@intel.com>
* ia64.h (ia64_opnd): Add new operand types.
+2012-08-21 David S. Miller <davem@davemloft.net>
+
+ * sparc.h (F3F4): New macro.
+
+2012-08-13 Ian Bolton <ian.bolton@arm.com>
Laurent Desnogues <laurent.desnogues@arm.com>
Jim MacArthur <jim.macarthur@arm.com>
Marcus Shawcroft <marcus.shawcroft@arm.com>
@@ -44,31 +829,31 @@
Sofiane Naci <sofiane.naci@arm.com>
Tejas Belagod <tejas.belagod@arm.com>
Yufeng Zhang <yufeng.zhang@arm.com>
+
+ * aarch64.h: New file.
+
+2012-08-13 Richard Sandiford <rdsandiford@googlemail.com>
Maciej W. Rozycki <macro@codesourcery.com>
+
+ * mips.h (mips_opcode): Add the exclusions field.
+ (OPCODE_IS_MEMBER): Remove macro.
+ (cpu_is_member): New inline function.
+ (opcode_is_member): Likewise.
+
+2012-07-31 Chao-Ying Fu <fu@mips.com>
Catherine Moore <clm@codesourcery.com>
Maciej W. Rozycki <macro@codesourcery.com>
- Adam Nemet <anemet@caviumnetworks.com>
- Maciej W. Rozycki <macro@codesourcery.com>
- Maciej W. Rozycki <macro@codesourcery.com>
- (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
- Joseph Myers <joseph@codesourcery.com>
- Ian Lance Taylor <ian@wasabisystems.com>
- Ben Elliston <bje@wasabisystems.com>
- David Ung <davidu@mips.com>
- Nigel Stephens <nigel@mips.com>
- David Ung <davidu@mips.com>
-2012-08-16 Ian Bolton <ian.bolton@arm.com>
- Laurent Desnogues <laurent.desnogues@arm.com>
- Jim MacArthur <jim.macarthur@arm.com>
- Marcus Shawcroft <marcus.shawcroft@arm.com>
- Nigel Stephens <nigel.stephens@arm.com>
- Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
- Richard Earnshaw <rearnsha@arm.com>
- Sofiane Naci <sofiane.naci@arm.com>
- Tejas Belagod <tejas.belagod@arm.com>
- Yufeng Zhang <yufeng.zhang@arm.com>
- * aarch64.h: New file.
+ * mips.h: Document microMIPS DSP ASE usage.
+ (MICROMIPSOP_MASK_DSPACC, MICROMIPSOP_SH_DSPACC): Update for
+ microMIPS DSP ASE support.
+ (MICROMIPSOP_MASK_DSPSFT, MICROMIPSOP_SH_DSPSFT): Likewise.
+ (MICROMIPSOP_MASK_SA3, MICROMIPSOP_SH_SA3): Likewise.
+ (MICROMIPSOP_MASK_SA4, MICROMIPSOP_SH_SA4): Likewise.
+ (MICROMIPSOP_MASK_IMM8, MICROMIPSOP_SH_IMM8): Likewise.
+ (MICROMIPSOP_MASK_IMM10, MICROMIPSOP_SH_IMM10): Likewise.
+ (MICROMIPSOP_MASK_WRDSP, MICROMIPSOP_SH_WRDSP): Likewise.
+ (MICROMIPSOP_MASK_BP, MICROMIPSOP_SH_BP): Likewise.
2012-07-06 Maciej W. Rozycki <macro@codesourcery.com>
@@ -142,7 +927,7 @@
(XRELEASE_PREFIX_OPCODE): Likewise.
2011-12-08 Andrew Pinski <apinski@cavium.com>
- Adam Nemet <anemet@caviumnetworks.com>
+ Adam Nemet <anemet@caviumnetworks.com>
* mips.h (INSN_CHIP_MASK): Update according to INSN_OCTEON2.
(INSN_OCTEON2): New macro.
@@ -173,7 +958,7 @@
F_FJFMAU, F_IMA, F_ASI_CACHE_SPARING): New flag bits.
2011-08-09 Chao-ying Fu <fu@mips.com>
- Maciej W. Rozycki <macro@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_3BITPOS, OP_SH_3BITPOS): New macros.
(OP_MASK_OFFSET12, OP_SH_OFFSET12): Redefine.
@@ -219,7 +1004,7 @@
(MICROMIPSOP_MASK_MAJOR, MICROMIPSOP_SH_MAJOR): Remove macros.
2011-07-24 Chao-ying Fu <fu@mips.com>
- Maciej W. Rozycki <macro@codesourcery.com>
+ Maciej W. Rozycki <macro@codesourcery.com>
* mips.h (OP_MASK_EXTLSB, OP_SH_EXTLSB): New macros.
(OP_MASK_STYPE, OP_SH_STYPE): Likewise.
@@ -782,7 +1567,7 @@
2008-11-28 Joshua Kinard <kumba@gentoo.org>
* mips.h: Define CPU_R14000, CPU_R16000.
- (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
+ (OPCODE_IS_MEMBER): Include R14000, R16000 in test.
2008-11-18 Catherine Moore <clm@codesourcery.com>
@@ -828,7 +1613,7 @@
2008-04-28 Adam Nemet <anemet@caviumnetworks.com>
- * mips.h (INSN_MACRO): Move it up to the the pinfo macros.
+ * mips.h (INSN_MACRO): Move it up to the pinfo macros.
(INSN2_M_FP_S, INSN2_M_FP_D): New pinfo2 macros.
2008-04-14 Edmar Wienskoski <edmar@freescale.com>
@@ -1021,9 +1806,9 @@
* i386.h: Replace CpuMNI with CpuSSSE3.
2006-09-26 Mark Shinwell <shinwell@codesourcery.com>
- Joseph Myers <joseph@codesourcery.com>
- Ian Lance Taylor <ian@wasabisystems.com>
- Ben Elliston <bje@wasabisystems.com>
+ Joseph Myers <joseph@codesourcery.com>
+ Ian Lance Taylor <ian@wasabisystems.com>
+ Ben Elliston <bje@wasabisystems.com>
* arm.h (ARM_CEXT_IWMMXT2, ARM_ARCH_IWMMXT2): Define.
@@ -1066,18 +1851,18 @@
* m68k.h (mcf_mask): Define.
2006-05-05 Thiemo Seufer <ths@mips.com>
- David Ung <davidu@mips.com>
+ David Ung <davidu@mips.com>
* mips.h (enum): Add macro M_CACHE_AB.
2006-05-04 Thiemo Seufer <ths@mips.com>
- Nigel Stephens <nigel@mips.com>
+ Nigel Stephens <nigel@mips.com>
David Ung <davidu@mips.com>
* mips.h: Add INSN_SMARTMIPS define.
2006-04-30 Thiemo Seufer <ths@mips.com>
- David Ung <davidu@mips.com>
+ David Ung <davidu@mips.com>
* mips.h: Defines udi bits and masks. Add description of
characters which may appear in the args field of udi
@@ -1602,6 +2387,12 @@
For older changes see ChangeLog-9103
+Copyright (C) 2004-2015 Free Software Foundation, Inc.
+
+Copying and distribution of this file, with or without modification,
+are permitted in any medium without royalty provided the copyright
+notice and this notice are preserved.
+
Local Variables:
mode: change-log
left-margin: 8
diff --git a/external/gpl3/binutils/dist/include/opcode/hppa.h b/external/gpl3/binutils/dist/include/opcode/hppa.h
index 90732064497..37972711530 100644
--- a/external/gpl3/binutils/dist/include/opcode/hppa.h
+++ b/external/gpl3/binutils/dist/include/opcode/hppa.h
@@ -1,7 +1,5 @@
/* Table of opcodes for the PA-RISC.
- Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000,
- 2001, 2002, 2003, 2004, 2005, 2006, 2009, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 1990-2015 Free Software Foundation, Inc.
Contributed by the Center for Software Science at the
University of Utah (pa-gdb-bugs@cs.utah.edu).
@@ -895,8 +893,8 @@ static const struct pa_opcode pa_opcodes[] =
{ "fstdx", 0x2c000200, 0xfc0013c0, "cxcCft,x(s,b)", pa11, FLAG_STRICT},
{ "fstdx", 0x2c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
{ "fstdx", 0x2c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
-{ "fstqx", 0x3c000200, 0xfc00dfc0, "cxft,x(b)", pa10, 0},
-{ "fstqx", 0x3c000200, 0xfc001fc0, "cxft,x(s,b)", pa10, 0},
+{ "fstqx", 0x3c000200, 0xfc00dfc0, "cXft,x(b)", pa10, 0},
+{ "fstqx", 0x3c000200, 0xfc001fc0, "cXft,x(s,b)", pa10, 0},
{ "fldws", 0x24001000, 0xfc00df80, "cm5(b),fT", pa10, FLAG_STRICT},
{ "fldws", 0x24001000, 0xfc001f80, "cm5(s,b),fT", pa10, FLAG_STRICT},
{ "fldws", 0x24001000, 0xfc00d380, "cmcc5(b),fT", pa11, FLAG_STRICT},
@@ -921,8 +919,8 @@ static const struct pa_opcode pa_opcodes[] =
{ "fstds", 0x2c001200, 0xfc0013c0, "cmcCft,5(s,b)", pa11, FLAG_STRICT},
{ "fstds", 0x2c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
{ "fstds", 0x2c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
-{ "fstqs", 0x3c001200, 0xfc00dfc0, "cmft,5(b)", pa10, 0},
-{ "fstqs", 0x3c001200, 0xfc001fc0, "cmft,5(s,b)", pa10, 0},
+{ "fstqs", 0x3c001200, 0xfc00dfc0, "cMft,5(b)", pa10, 0},
+{ "fstqs", 0x3c001200, 0xfc001fc0, "cMft,5(s,b)", pa10, 0},
{ "fadd", 0x30000600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
{ "fadd", 0x38000600, 0xfc00e720, "IfA,fB,fT", pa10, 0},
{ "fsub", 0x30002600, 0xfc00e7e0, "Ffa,fb,fT", pa10, 0},
diff --git a/external/gpl3/binutils/dist/include/opcode/mips.h b/external/gpl3/binutils/dist/include/opcode/mips.h
index 419ba60690b..a8845b6a19a 100644
--- a/external/gpl3/binutils/dist/include/opcode/mips.h
+++ b/external/gpl3/binutils/dist/include/opcode/mips.h
@@ -1,7 +1,5 @@
/* mips.h. Mips opcode list for GDB, the GNU debugger.
- Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002,
- 2003, 2004, 2005, 2008, 2009, 2010
- Free Software Foundation, Inc.
+ Copyright (C) 1993-2015 Free Software Foundation, Inc.
Contributed by Ralph Campbell and OSF
Commented and modified by Ian Lance Taylor, Cygnus Support
@@ -212,6 +210,10 @@
#define OP_OP_SDC2 0x3e
#define OP_OP_SDC3 0x3f /* a.k.a. sd */
+/* MIPS VIRT ASE */
+#define OP_MASK_CODE10 0x3ff
+#define OP_SH_CODE10 11
+
/* Values in the 'VSEL' field. */
#define MDMX_FMTSEL_IMM_QH 0x1d
#define MDMX_FMTSEL_IMM_OB 0x1e
@@ -255,8 +257,6 @@
of the operand handling in GAS. The fields below only exist
in the microMIPS encoding, so define each one to have an empty
range. */
-#define OP_MASK_CODE10 0
-#define OP_SH_CODE10 0
#define OP_MASK_TRAP 0
#define OP_SH_TRAP 0
#define OP_MASK_OFFSET10 0
@@ -277,8 +277,6 @@
#define OP_SH_MG 0
#define OP_MASK_MH 0
#define OP_SH_MH 0
-#define OP_MASK_MI 0
-#define OP_SH_MI 0
#define OP_MASK_MJ 0
#define OP_SH_MJ 0
#define OP_MASK_ML 0
@@ -328,6 +326,394 @@
#define OP_MASK_IMMY 0
#define OP_SH_IMMY 0
+/* Enhanced VA Scheme */
+#define OP_SH_EVAOFFSET 7
+#define OP_MASK_EVAOFFSET 0x1ff
+
+/* Enumerates the various types of MIPS operand. */
+enum mips_operand_type {
+ /* Described by mips_int_operand. */
+ OP_INT,
+
+ /* Described by mips_mapped_int_operand. */
+ OP_MAPPED_INT,
+
+ /* Described by mips_msb_operand. */
+ OP_MSB,
+
+ /* Described by mips_reg_operand. */
+ OP_REG,
+
+ /* Like OP_REG, but can be omitted if the register is the same as the
+ previous operand. */
+ OP_OPTIONAL_REG,
+
+ /* Described by mips_reg_pair_operand. */
+ OP_REG_PAIR,
+
+ /* Described by mips_pcrel_operand. */
+ OP_PCREL,
+
+ /* A performance register. The field is 5 bits in size, but the supported
+ values are much more restricted. */
+ OP_PERF_REG,
+
+ /* The final operand in a microMIPS ADDIUSP instruction. It mostly acts
+ as a normal 9-bit signed offset that is multiplied by four, but there
+ are four special cases:
+
+ -2 * 4 => -258 * 4
+ -1 * 4 => -257 * 4
+ 0 * 4 => 256 * 4
+ 1 * 4 => 257 * 4. */
+ OP_ADDIUSP_INT,
+
+ /* The target of a (D)CLO or (D)CLZ instruction. The operand spans two
+ 5-bit register fields, both of which must be set to the destination
+ register. */
+ OP_CLO_CLZ_DEST,
+
+ /* A register list for a microMIPS LWM or SWM instruction. The operand
+ size determines whether the 16-bit or 32-bit encoding is required. */
+ OP_LWM_SWM_LIST,
+
+ /* The register list for an emulated MIPS16 ENTRY or EXIT instruction. */
+ OP_ENTRY_EXIT_LIST,
+
+ /* The register list and frame size for a MIPS16 SAVE or RESTORE
+ instruction. */
+ OP_SAVE_RESTORE_LIST,
+
+ /* A 10-bit field VVVVVNNNNN used for octobyte and quadhalf instructions:
+
+ V Meaning
+ ----- -------
+ 0EEE0 8 copies of $vN[E], OB format
+ 0EE01 4 copies of $vN[E], QH format
+ 10110 all 8 elements of $vN, OB format
+ 10101 all 4 elements of $vN, QH format
+ 11110 8 copies of immediate N, OB format
+ 11101 4 copies of immediate N, QH format. */
+ OP_MDMX_IMM_REG,
+
+ /* A register operand that must match the destination register. */
+ OP_REPEAT_DEST_REG,
+
+ /* A register operand that must match the previous register. */
+ OP_REPEAT_PREV_REG,
+
+ /* $pc, which has no encoding in the architectural instruction. */
+ OP_PC,
+
+ /* A 4-bit XYZW channel mask or 2-bit XYZW index; the size determines
+ which. */
+ OP_VU0_SUFFIX,
+
+ /* Like OP_VU0_SUFFIX, but used when the operand's value has already
+ been set. Any suffix used here must match the previous value. */
+ OP_VU0_MATCH_SUFFIX,
+
+ /* An index selected by an integer, e.g. [1]. */
+ OP_IMM_INDEX,
+
+ /* An index selected by a register, e.g. [$2]. */
+ OP_REG_INDEX,
+
+ /* The operand spans two 5-bit register fields, both of which must be set to
+ the source register. */
+ OP_SAME_RS_RT,
+
+ /* Described by mips_prev_operand. */
+ OP_CHECK_PREV,
+
+ /* A register operand that must not be zero. */
+ OP_NON_ZERO_REG
+};
+
+/* Enumerates the types of MIPS register. */
+enum mips_reg_operand_type {
+ /* General registers $0-$31. Software names like $at can also be used. */
+ OP_REG_GP,
+
+ /* Floating-point registers $f0-$f31. */
+ OP_REG_FP,
+
+ /* Coprocessor condition code registers $cc0-$cc7. FPU condition codes
+ can also be written $fcc0-$fcc7. */
+ OP_REG_CCC,
+
+ /* FPRs used in a vector capacity. They can be written $f0-$f31
+ or $v0-$v31, although the latter form is not used for the VR5400
+ vector instructions. */
+ OP_REG_VEC,
+
+ /* DSP accumulator registers $ac0-$ac3. */
+ OP_REG_ACC,
+
+ /* Coprocessor registers $0-$31. Mnemonic names like c0_cause can
+ also be used in some contexts. */
+ OP_REG_COPRO,
+
+ /* Hardware registers $0-$31. Mnemonic names like hwr_cpunum can
+ also be used in some contexts. */
+ OP_REG_HW,
+
+ /* Floating-point registers $vf0-$vf31. */
+ OP_REG_VF,
+
+ /* Integer registers $vi0-$vi31. */
+ OP_REG_VI,
+
+ /* R5900 VU0 registers $I, $Q, $R and $ACC. */
+ OP_REG_R5900_I,
+ OP_REG_R5900_Q,
+ OP_REG_R5900_R,
+ OP_REG_R5900_ACC,
+
+ /* MSA registers $w0-$w31. */
+ OP_REG_MSA,
+
+ /* MSA control registers $0-$31. */
+ OP_REG_MSA_CTRL
+};
+
+/* Base class for all operands. */
+struct mips_operand
+{
+ /* The type of the operand. */
+ enum mips_operand_type type;
+
+ /* The operand occupies SIZE bits of the instruction, starting at LSB. */
+ unsigned short size;
+ unsigned short lsb;
+};
+
+/* Describes an integer operand with a regular encoding pattern. */
+struct mips_int_operand
+{
+ struct mips_operand root;
+
+ /* The low ROOT.SIZE bits of MAX_VAL encodes (MAX_VAL + BIAS) << SHIFT.
+ The cyclically previous field value encodes 1 << SHIFT less than that,
+ and so on. E.g.
+
+ - for { { T, 4, L }, 14, 0, 0 }, field values 0...14 encode themselves,
+ but 15 encodes -1.
+
+ - { { T, 8, L }, 127, 0, 2 } is a normal signed 8-bit operand that is
+ shifted left two places.
+
+ - { { T, 3, L }, 8, 0, 0 } is a normal unsigned 3-bit operand except
+ that 0 encodes 8.
+
+ - { { ... }, 0, 1, 3 } means that N encodes (N + 1) << 3. */
+ unsigned int max_val;
+ int bias;
+ unsigned int shift;
+
+ /* True if the operand should be printed as hex rather than decimal. */
+ bfd_boolean print_hex;
+};
+
+/* Uses a lookup table to describe a small integer operand. */
+struct mips_mapped_int_operand
+{
+ struct mips_operand root;
+
+ /* Maps each encoding value to the integer that it represents. */
+ const int *int_map;
+
+ /* True if the operand should be printed as hex rather than decimal. */
+ bfd_boolean print_hex;
+};
+
+/* An operand that encodes the most significant bit position of a bitfield.
+ Given a bitfield that spans bits [MSB, LSB], some operands of this type
+ encode MSB directly while others encode MSB - LSB. Each operand of this
+ type is preceded by an integer operand that specifies LSB.
+
+ The assembly form varies between instructions. For some instructions,
+ such as EXT, the operand is written as the bitfield size. For others,
+ such as EXTS, it is written in raw MSB - LSB form. */
+struct mips_msb_operand
+{
+ struct mips_operand root;
+
+ /* The assembly-level operand encoded by a field value of 0. */
+ int bias;
+
+ /* True if the operand encodes MSB directly, false if it encodes
+ MSB - LSB. */
+ bfd_boolean add_lsb;
+
+ /* The maximum value of MSB + 1. */
+ unsigned int opsize;
+};
+
+/* Describes a single register operand. */
+struct mips_reg_operand
+{
+ struct mips_operand root;
+
+ /* The type of register. */
+ enum mips_reg_operand_type reg_type;
+
+ /* If nonnull, REG_MAP[N] gives the register associated with encoding N,
+ otherwise the encoding is the same as the register number. */
+ const unsigned char *reg_map;
+};
+
+/* Describes an operand that which must match a condition based on the
+ previous operand. */
+struct mips_check_prev_operand
+{
+ struct mips_operand root;
+
+ bfd_boolean greater_than_ok;
+ bfd_boolean less_than_ok;
+ bfd_boolean equal_ok;
+ bfd_boolean zero_ok;
+};
+
+/* Describes an operand that encodes a pair of registers. */
+struct mips_reg_pair_operand
+{
+ struct mips_operand root;
+
+ /* The type of register. */
+ enum mips_reg_operand_type reg_type;
+
+ /* Encoding N represents REG1_MAP[N], REG2_MAP[N]. */
+ unsigned char *reg1_map;
+ unsigned char *reg2_map;
+};
+
+/* Describes an operand that is calculated relative to a base PC.
+ The base PC is usually the address of the following instruction,
+ but the rules for MIPS16 instructions like ADDIUPC are more complicated. */
+struct mips_pcrel_operand
+{
+ /* Encodes the offset. */
+ struct mips_int_operand root;
+
+ /* The low ALIGN_LOG2 bits of the base PC are cleared to give PC',
+ which is then added to the offset encoded by ROOT. */
+ unsigned int align_log2 : 8;
+
+ /* If INCLUDE_ISA_BIT, the ISA bit of the original base PC is then
+ reinstated. This is true for jumps and branches and false for
+ PC-relative data instructions. */
+ unsigned int include_isa_bit : 1;
+
+ /* If FLIP_ISA_BIT, the ISA bit of the result is inverted.
+ This is true for JALX and false otherwise. */
+ unsigned int flip_isa_bit : 1;
+};
+
+/* Return true if the assembly syntax allows OPERAND to be omitted. */
+
+static inline bfd_boolean
+mips_optional_operand_p (const struct mips_operand *operand)
+{
+ return (operand->type == OP_OPTIONAL_REG
+ || operand->type == OP_REPEAT_PREV_REG);
+}
+
+/* Return a version of INSN in which the field specified by OPERAND
+ has value UVAL. */
+
+static inline unsigned int
+mips_insert_operand (const struct mips_operand *operand, unsigned int insn,
+ unsigned int uval)
+{
+ unsigned int mask;
+
+ mask = (1 << operand->size) - 1;
+ insn &= ~(mask << operand->lsb);
+ insn |= (uval & mask) << operand->lsb;
+ return insn;
+}
+
+/* Extract OPERAND from instruction INSN. */
+
+static inline unsigned int
+mips_extract_operand (const struct mips_operand *operand, unsigned int insn)
+{
+ return (insn >> operand->lsb) & ((1 << operand->size) - 1);
+}
+
+/* UVAL is the value encoded by OPERAND. Return it in signed form. */
+
+static inline int
+mips_signed_operand (const struct mips_operand *operand, unsigned int uval)
+{
+ unsigned int sign_bit, mask;
+
+ mask = (1 << operand->size) - 1;
+ sign_bit = 1 << (operand->size - 1);
+ return ((uval + sign_bit) & mask) - sign_bit;
+}
+
+/* Return the integer that OPERAND encodes as UVAL. */
+
+static inline int
+mips_decode_int_operand (const struct mips_int_operand *operand,
+ unsigned int uval)
+{
+ uval |= (operand->max_val - uval) & -(1 << operand->root.size);
+ uval += operand->bias;
+ uval <<= operand->shift;
+ return uval;
+}
+
+/* Return the maximum value that can be encoded by OPERAND. */
+
+static inline int
+mips_int_operand_max (const struct mips_int_operand *operand)
+{
+ return (operand->max_val + operand->bias) << operand->shift;
+}
+
+/* Return the minimum value that can be encoded by OPERAND. */
+
+static inline int
+mips_int_operand_min (const struct mips_int_operand *operand)
+{
+ unsigned int mask;
+
+ mask = (1 << operand->root.size) - 1;
+ return mips_int_operand_max (operand) - (mask << operand->shift);
+}
+
+/* Return the register that OPERAND encodes as UVAL. */
+
+static inline int
+mips_decode_reg_operand (const struct mips_reg_operand *operand,
+ unsigned int uval)
+{
+ if (operand->reg_map)
+ uval = operand->reg_map[uval];
+ return uval;
+}
+
+/* PC-relative operand OPERAND has value UVAL and is relative to BASE_PC.
+ Return the address that it encodes. */
+
+static inline bfd_vma
+mips_decode_pcrel_operand (const struct mips_pcrel_operand *operand,
+ bfd_vma base_pc, unsigned int uval)
+{
+ bfd_vma addr;
+
+ addr = base_pc & -(1 << operand->align_log2);
+ addr += mips_decode_int_operand (&operand->root, uval);
+ if (operand->include_isa_bit)
+ addr |= base_pc & 1;
+ if (operand->flip_isa_bit)
+ addr ^= 1;
+ return addr;
+}
+
/* This structure holds information for a particular instruction. */
struct mips_opcode
@@ -355,6 +741,9 @@ struct mips_opcode
/* A collection of bits describing the instruction sets of which this
instruction or macro is a member. */
unsigned long membership;
+ /* A collection of bits describing the ASE of which this instruction
+ or macro is a member. */
+ unsigned long ase;
/* A collection of bits describing the instruction sets of which this
instruction or macro is not a member. */
unsigned long exclusions;
@@ -368,10 +757,11 @@ struct mips_opcode
Each of these characters corresponds to a mask field defined above.
- "1" 5 bit sync type (OP_*_SHAMT)
+ "1" 5 bit sync type (OP_*_STYPE)
"<" 5 bit shift amount (OP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
"a" 26 bit target address (OP_*_TARGET)
+ "+i" likewise, but flips bit 0
"b" 5 bit base register (OP_*_RS)
"c" 10 bit breakpoint code (OP_*_CODE)
"d" 5 bit destination register specifier (OP_*_RD)
@@ -379,7 +769,6 @@ struct mips_opcode
"i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
"j" 16 bit signed immediate (OP_*_DELTA)
"k" 5 bit cache opcode in target register position (OP_*_CACHE)
- Also used for immediate operands in vr5400 vector insns.
"o" 16 bit signed offset (OP_*_DELTA)
"p" 16 bit PC relative branch target address (OP_*_DELTA)
"q" 10 bit extra breakpoint code (OP_*_CODE2)
@@ -438,26 +827,43 @@ struct mips_opcode
"P" 5 bit performance-monitor register (OP_*_PERFREG)
"e" 5 bit vector register byte specifier (OP_*_VECBYTE)
"%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
- see also "k" above
- "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
- for pretty-printing in disassembly only.
Macro instructions:
"A" General 32 bit expression
"I" 32 bit immediate (value placed in imm_expr).
- "+I" 32 bit immediate (value placed in imm2_expr).
"F" 64 bit floating point constant in .rdata
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
- MDMX instruction operands (note that while these use the FP register
- fields, they accept both $fN and $vN names for the registers):
- "O" MDMX alignment offset (OP_*_ALN)
- "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
- "X" MDMX destination register (OP_*_FD)
- "Y" MDMX source register (OP_*_FS)
- "Z" MDMX source register (OP_*_FT)
+ MDMX and VR5400 instruction operands (note that while these use the
+ FP register fields, the MDMX instructions accept both $fN and $vN names
+ for the registers):
+ "O" alignment offset (OP_*_ALN)
+ "Q" vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
+ "X" destination register (OP_*_FD)
+ "Y" source register (OP_*_FS)
+ "Z" source register (OP_*_FT)
+
+ R5900 VU0 Macromode instructions:
+ "+5" 5 bit floating point register (FD)
+ "+6" 5 bit floating point register (FS)
+ "+7" 5 bit floating point register (FT)
+ "+8" 5 bit integer register (FD)
+ "+9" 5 bit integer register (FS)
+ "+0" 5 bit integer register (FT)
+ "+K" match an existing 4-bit channel mask starting at bit 21
+ "+L" 2-bit channel index starting at bit 21
+ "+M" 2-bit channel index starting at bit 23
+ "+N" match an existing 2-bit channel index starting at bit 0
+ "+f" 15 bit immediate for VCALLMS
+ "+g" 5 bit signed immediate for VIADDI
+ "+m" $ACC register (syntax only)
+ "+q" $Q register (syntax only)
+ "+r" $R register (syntax only)
+ "+y" $I register (syntax only)
+ "#+" "++" decorator in ($reg++) sequence
+ "#-" "--" decorator in (--$reg) sequence
DSP ASE usage:
"2" 2 bit unsigned immediate for byte align (OP_*_BP)
@@ -480,12 +886,14 @@ struct mips_opcode
"&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
"g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
"+t" 5 bit coprocessor 0 destination register (OP_*_RT)
- "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
MCU ASE usage:
"~" 12 bit offset (OP_*_OFFSET12)
"\" 3 bit position for aset and aclr (OP_*_3BITPOS)
+ VIRT ASE usage:
+ "+J" 10-bit hypcall code (OP_*CODE10)
+
UDI immediates:
"+1" UDI immediate bits 6-10
"+2" UDI immediate bits 6-15
@@ -500,11 +908,10 @@ struct mips_opcode
"+P" Position field of cins/exts aliasing cins32/exts32. Matches if
32 <= pos < 64, otherwise skips to next candidate.
"+Q" Immediate field of seqi/snei. Enforces -512 <= imm < 512.
- "+s" Length-minus-one field of cins/exts. Enforces: 0 <= lenm1 < 32.
- "+S" Length-minus-one field of cins32/exts32 or cins/exts aliasing
- cint32/exts32. Enforces non-negative value and that
- pos + lenm1 < 32 or pos + lenm1 < 64 depending whether previous
- position field is "+p" or "+P".
+ "+s" Length-minus-one field of cins32/exts32. Requires msb position
+ of the field to be <= 31.
+ "+S" Length-minus-one field of cins/exts. Requires msb position
+ of the field to be <= 63.
Loongson-3A:
"+a" 8-bit signed offset in bit 6 (OP_*_OFFSET_A)
@@ -513,93 +920,145 @@ struct mips_opcode
"+z" 5-bit rz register (OP_*_RZ)
"+Z" 5-bit fz register (OP_*_FZ)
+ Enhanced VA Scheme:
+ "+j" 9-bit signed offset in bit 7 (OP_*_EVAOFFSET)
+
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 4-bit vector element index at bit 16
+ "+u" 3-bit vector element index at bit 16
+ "+v" 2-bit vector element index at bit 16
+ "+w" 1-bit vector element index at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
+ MIPS R6:
+ "+:" 11-bit mask at bit 0
+ "+'" 26 bit PC relative branch target address
+ "+"" 21 bit PC relative branch target address
+ "+;" 5 bit same register in both OP_*_RS and OP_*_RT
+ "+I" 2bit unsigned bit position at bit 6
+ "+O" 3bit unsigned bit position at bit 6
+ "+R" must be program counter
+ "-a" (-262144 .. 262143) << 2 at bit 0
+ "-b" (-131072 .. 131071) << 3 at bit 0
+ "-d" Same as destination register GP
+ "-s" 5 bit source register specifier (OP_*_RS) not $0
+ "-t" 5 bit source register specifier (OP_*_RT) not $0
+ "-u" 5 bit source register specifier (OP_*_RT) greater than OP_*_RS
+ "-v" 5 bit source register specifier (OP_*_RT) not $0 not OP_*_RS
+ "-w" 5 bit source register specifier (OP_*_RT) less than or equal to OP_*_RS
+ "-x" 5 bit source register specifier (OP_*_RT) greater than or
+ equal to OP_*_RS
+ "-y" 5 bit source register specifier (OP_*_RT) not $0 less than OP_*_RS
+ "-A" symbolic offset (-262144 .. 262143) << 2 at bit 0
+ "-B" symbolic offset (-131072 .. 131071) << 3 at bit 0
+
Other:
"()" parens surrounding optional value
"," separates operands
- "[]" brackets around index for vector-op scalar operand specifier (vr5400)
"+" Start of extension sequence.
Characters used so far, for quick reference when adding more:
"1234567890"
- "%[]<>(),+:'@!$*&\~"
+ "%[]<>(),+-:'@!#$*&\~"
"ABCDEFGHIJKLMNOPQRSTUVWXYZ"
"abcdefghijklopqrstuvwxz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
- "1234"
- "ABCDEFGHIPQSTXZ"
- "abcpstxz"
+ "1234567890"
+ "~!@#$%^&*|:'";"
+ "ABCEFGHIJKLMNOPQRSTUVWXZ"
+ "abcdefghijklmnopqrstuvwxyz"
+
+ Extension character sequences used so far ("-" followed by the
+ following), for quick reference when adding more:
+ "AB"
+ "abdstuvwxy"
*/
/* These are the bits which may be set in the pinfo field of an
instructions, if it is not equal to INSN_MACRO. */
-/* Modifies the general purpose register in OP_*_RD. */
-#define INSN_WRITE_GPR_D 0x00000001
-/* Modifies the general purpose register in OP_*_RT. */
-#define INSN_WRITE_GPR_T 0x00000002
+/* Writes to operand number N. */
+#define INSN_WRITE_SHIFT 0
+#define INSN_WRITE_1 0x00000001
+#define INSN_WRITE_2 0x00000002
+#define INSN_WRITE_ALL 0x00000003
+/* Reads from operand number N. */
+#define INSN_READ_SHIFT 2
+#define INSN_READ_1 0x00000004
+#define INSN_READ_2 0x00000008
+#define INSN_READ_3 0x00000010
+#define INSN_READ_4 0x00000020
+#define INSN_READ_ALL 0x0000003c
/* Modifies general purpose register 31. */
-#define INSN_WRITE_GPR_31 0x00000004
-/* Modifies the floating point register in OP_*_FD. */
-#define INSN_WRITE_FPR_D 0x00000008
-/* Modifies the floating point register in OP_*_FS. */
-#define INSN_WRITE_FPR_S 0x00000010
-/* Modifies the floating point register in OP_*_FT. */
-#define INSN_WRITE_FPR_T 0x00000020
-/* Reads the general purpose register in OP_*_RS. */
-#define INSN_READ_GPR_S 0x00000040
-/* Reads the general purpose register in OP_*_RT. */
-#define INSN_READ_GPR_T 0x00000080
-/* Reads the floating point register in OP_*_FS. */
-#define INSN_READ_FPR_S 0x00000100
-/* Reads the floating point register in OP_*_FT. */
-#define INSN_READ_FPR_T 0x00000200
-/* Reads the floating point register in OP_*_FR. */
-#define INSN_READ_FPR_R 0x00000400
+#define INSN_WRITE_GPR_31 0x00000040
/* Modifies coprocessor condition code. */
-#define INSN_WRITE_COND_CODE 0x00000800
+#define INSN_WRITE_COND_CODE 0x00000080
/* Reads coprocessor condition code. */
-#define INSN_READ_COND_CODE 0x00001000
+#define INSN_READ_COND_CODE 0x00000100
/* TLB operation. */
-#define INSN_TLB 0x00002000
+#define INSN_TLB 0x00000200
/* Reads coprocessor register other than floating point register. */
-#define INSN_COP 0x00004000
-/* Instruction loads value from memory, requiring delay. */
-#define INSN_LOAD_MEMORY_DELAY 0x00008000
-/* Instruction loads value from coprocessor, requiring delay. */
-#define INSN_LOAD_COPROC_DELAY 0x00010000
+#define INSN_COP 0x00000400
+/* Instruction loads value from memory. */
+#define INSN_LOAD_MEMORY 0x00000800
+/* Instruction loads value from coprocessor, (may require delay). */
+#define INSN_LOAD_COPROC 0x00001000
/* Instruction has unconditional branch delay slot. */
-#define INSN_UNCOND_BRANCH_DELAY 0x00020000
+#define INSN_UNCOND_BRANCH_DELAY 0x00002000
/* Instruction has conditional branch delay slot. */
-#define INSN_COND_BRANCH_DELAY 0x00040000
+#define INSN_COND_BRANCH_DELAY 0x00004000
/* Conditional branch likely: if branch not taken, insn nullified. */
-#define INSN_COND_BRANCH_LIKELY 0x00080000
-/* Moves to coprocessor register, requiring delay. */
-#define INSN_COPROC_MOVE_DELAY 0x00100000
+#define INSN_COND_BRANCH_LIKELY 0x00008000
+/* Moves to coprocessor register, (may require delay). */
+#define INSN_COPROC_MOVE 0x00010000
/* Loads coprocessor register from memory, requiring delay. */
-#define INSN_COPROC_MEMORY_DELAY 0x00200000
+#define INSN_COPROC_MEMORY_DELAY 0x00020000
/* Reads the HI register. */
-#define INSN_READ_HI 0x00400000
+#define INSN_READ_HI 0x00040000
/* Reads the LO register. */
-#define INSN_READ_LO 0x00800000
+#define INSN_READ_LO 0x00080000
/* Modifies the HI register. */
-#define INSN_WRITE_HI 0x01000000
+#define INSN_WRITE_HI 0x00100000
/* Modifies the LO register. */
-#define INSN_WRITE_LO 0x02000000
+#define INSN_WRITE_LO 0x00200000
/* Not to be placed in a branch delay slot, either architecturally
or for ease of handling (such as with instructions that take a trap). */
-#define INSN_NO_DELAY_SLOT 0x04000000
+#define INSN_NO_DELAY_SLOT 0x00400000
/* Instruction stores value into memory. */
-#define INSN_STORE_MEMORY 0x08000000
+#define INSN_STORE_MEMORY 0x00800000
/* Instruction uses single precision floating point. */
-#define FP_S 0x10000000
+#define FP_S 0x01000000
/* Instruction uses double precision floating point. */
-#define FP_D 0x20000000
+#define FP_D 0x02000000
/* Instruction is part of the tx39's integer multiply family. */
-#define INSN_MULT 0x40000000
-/* Modifies the general purpose register in MICROMIPSOP_*_RS. */
-#define INSN_WRITE_GPR_S 0x80000000
+#define INSN_MULT 0x04000000
+/* Reads general purpose register 24. */
+#define INSN_READ_GPR_24 0x08000000
+/* Writes to general purpose register 24. */
+#define INSN_WRITE_GPR_24 0x10000000
+/* A user-defined instruction. */
+#define INSN_UDI 0x20000000
/* Instruction is actually a macro. It should be ignored by the
disassembler, and requires special treatment by the assembler. */
#define INSN_MACRO 0xffffffff
@@ -621,62 +1080,28 @@ struct mips_opcode
only be set for macros. For instructions, FP_D in pinfo carries the
same information. */
#define INSN2_M_FP_D 0x00000010
-/* Modifies the general purpose register in OP_*_RZ. */
-#define INSN2_WRITE_GPR_Z 0x00000020
-/* Modifies the floating point register in OP_*_FZ. */
-#define INSN2_WRITE_FPR_Z 0x00000040
-/* Reads the general purpose register in OP_*_RZ. */
-#define INSN2_READ_GPR_Z 0x00000080
-/* Reads the floating point register in OP_*_FZ. */
-#define INSN2_READ_FPR_Z 0x00000100
-/* Reads the general purpose register in OP_*_RD. */
-#define INSN2_READ_GPR_D 0x00000200
-
-
/* Instruction has a branch delay slot that requires a 16-bit instruction. */
-#define INSN2_BRANCH_DELAY_16BIT 0x00000400
+#define INSN2_BRANCH_DELAY_16BIT 0x00000020
/* Instruction has a branch delay slot that requires a 32-bit instruction. */
-#define INSN2_BRANCH_DELAY_32BIT 0x00000800
-/* Reads the floating point register in MICROMIPSOP_*_FD. */
-#define INSN2_READ_FPR_D 0x00001000
-/* Modifies the general purpose register in MICROMIPSOP_*_MB. */
-#define INSN2_WRITE_GPR_MB 0x00002000
-/* Reads the general purpose register in MICROMIPSOP_*_MC. */
-#define INSN2_READ_GPR_MC 0x00004000
-/* Reads/writes the general purpose register in MICROMIPSOP_*_MD. */
-#define INSN2_MOD_GPR_MD 0x00008000
-/* Reads the general purpose register in MICROMIPSOP_*_ME. */
-#define INSN2_READ_GPR_ME 0x00010000
-/* Reads/writes the general purpose register in MICROMIPSOP_*_MF. */
-#define INSN2_MOD_GPR_MF 0x00020000
-/* Reads the general purpose register in MICROMIPSOP_*_MG. */
-#define INSN2_READ_GPR_MG 0x00040000
-/* Reads the general purpose register in MICROMIPSOP_*_MJ. */
-#define INSN2_READ_GPR_MJ 0x00080000
-/* Modifies the general purpose register in MICROMIPSOP_*_MJ. */
-#define INSN2_WRITE_GPR_MJ 0x00100000
-/* Reads the general purpose register in MICROMIPSOP_*_MP. */
-#define INSN2_READ_GPR_MP 0x00200000
-/* Modifies the general purpose register in MICROMIPSOP_*_MP. */
-#define INSN2_WRITE_GPR_MP 0x00400000
-/* Reads the general purpose register in MICROMIPSOP_*_MQ. */
-#define INSN2_READ_GPR_MQ 0x00800000
-/* Reads/Writes the stack pointer ($29). */
-#define INSN2_MOD_SP 0x01000000
+#define INSN2_BRANCH_DELAY_32BIT 0x00000040
+/* Writes to the stack pointer ($29). */
+#define INSN2_WRITE_SP 0x00000080
+/* Reads from the stack pointer ($29). */
+#define INSN2_READ_SP 0x00000100
/* Reads the RA ($31) register. */
-#define INSN2_READ_GPR_31 0x02000000
-/* Reads the global pointer ($28). */
-#define INSN2_READ_GP 0x04000000
+#define INSN2_READ_GPR_31 0x00000200
/* Reads the program counter ($pc). */
-#define INSN2_READ_PC 0x08000000
+#define INSN2_READ_PC 0x00000400
/* Is an unconditional branch insn. */
-#define INSN2_UNCOND_BRANCH 0x10000000
+#define INSN2_UNCOND_BRANCH 0x00000800
/* Is a conditional branch insn. */
-#define INSN2_COND_BRANCH 0x20000000
-/* Modifies the general purpose registers in MICROMIPSOP_*_MH/I. */
-#define INSN2_WRITE_GPR_MHI 0x40000000
-/* Reads the general purpose registers in MICROMIPSOP_*_MM/N. */
-#define INSN2_READ_GPR_MMN 0x80000000
+#define INSN2_COND_BRANCH 0x00001000
+/* Reads from $16. This is true of the MIPS16 0x6500 nop. */
+#define INSN2_READ_GPR_16 0x00002000
+/* Has an "\.x?y?z?w?" suffix based on mips_vu0_channel_mask. */
+#define INSN2_VU0_CHANNEL_SUFFIX 0x00004000
+/* Instruction has a forbidden slot. */
+#define INSN2_FORBIDDEN_SLOT 0x00008000
/* Masks used to mark instructions to indicate which MIPS ISA level
they were introduced in. INSN_ISA_MASK masks an enumeration that
@@ -684,7 +1109,7 @@ struct mips_opcode
word constructed using these macros is a bitmask of the remaining
INSN_* values below. */
-#define INSN_ISA_MASK 0x0000000ful
+#define INSN_ISA_MASK 0x0000001ful
/* We cannot start at zero due to ISA_UNKNOWN below. */
#define INSN_ISA1 1
@@ -694,28 +1119,75 @@ struct mips_opcode
#define INSN_ISA5 5
#define INSN_ISA32 6
#define INSN_ISA32R2 7
-#define INSN_ISA64 8
-#define INSN_ISA64R2 9
+#define INSN_ISA32R3 8
+#define INSN_ISA32R5 9
+#define INSN_ISA32R6 10
+#define INSN_ISA64 11
+#define INSN_ISA64R2 12
+#define INSN_ISA64R3 13
+#define INSN_ISA64R5 14
+#define INSN_ISA64R6 15
/* Below this point the INSN_* values correspond to combinations of ISAs.
They are only for use in the opcodes table to indicate membership of
a combination of ISAs that cannot be expressed using the usual inclusion
ordering on the above INSN_* values. */
-#define INSN_ISA3_32 10
-#define INSN_ISA3_32R2 11
-#define INSN_ISA4_32 12
-#define INSN_ISA4_32R2 13
-#define INSN_ISA5_32R2 14
-
-/* Given INSN_ISA* values X and Y, where X ranges over INSN_ISA1 through
- INSN_ISA5_32R2 and Y ranges over INSN_ISA1 through INSN_ISA64R2,
- this table describes whether at least one of the ISAs described by X
- is/are implemented by ISA Y. (Think of Y as the ISA level supported by
- a particular core and X as the ISA level(s) at which a certain instruction
- is defined.) The ISA(s) described by X is/are implemented by Y iff
- (mips_isa_table[(Y & INSN_ISA_MASK) - 1] >> ((X & INSN_ISA_MASK) - 1)) & 1
- is non-zero. */
-static const unsigned int mips_isa_table[] =
- { 0x0001, 0x0003, 0x0607, 0x1e0f, 0x3e1f, 0x0a23, 0x3e63, 0x3ebf, 0x3fff };
+#define INSN_ISA3_32 16
+#define INSN_ISA3_32R2 17
+#define INSN_ISA4_32 18
+#define INSN_ISA4_32R2 19
+#define INSN_ISA5_32R2 20
+
+/* The R6 definitions shown below state that they support all previous ISAs.
+ This is not actually true as some instructions are removed in R6.
+ The problem is that the removed instructions in R6 come from different
+ ISAs. One approach to solve this would be to describe in the membership
+ field of the opcode table the different ISAs an instruction belongs to.
+ This would require us to create a large amount of different ISA
+ combinations which is hard to manage. A cleaner approach (which is
+ implemented here) is to say that R6 is an extension of R5 and then to
+ deal with the removed instructions by adding instruction exclusions
+ for R6 in the opcode table. */
+
+/* Bit INSN_ISA<X> - 1 of INSN_UPTO<Y> is set if ISA Y includes ISA X. */
+
+#define ISAF(X) (1 << (INSN_ISA##X - 1))
+#define INSN_UPTO1 ISAF(1)
+#define INSN_UPTO2 INSN_UPTO1 | ISAF(2)
+#define INSN_UPTO3 INSN_UPTO2 | ISAF(3) | ISAF(3_32) | ISAF(3_32R2)
+#define INSN_UPTO4 INSN_UPTO3 | ISAF(4) | ISAF(4_32) | ISAF(4_32R2)
+#define INSN_UPTO5 INSN_UPTO4 | ISAF(5) | ISAF(5_32R2)
+#define INSN_UPTO32 INSN_UPTO2 | ISAF(32) | ISAF(3_32) | ISAF(4_32)
+#define INSN_UPTO32R2 INSN_UPTO32 | ISAF(32R2) \
+ | ISAF(3_32R2) | ISAF(4_32R2) | ISAF(5_32R2)
+#define INSN_UPTO32R3 INSN_UPTO32R2 | ISAF(32R3)
+#define INSN_UPTO32R5 INSN_UPTO32R3 | ISAF(32R5)
+#define INSN_UPTO32R6 INSN_UPTO32R5 | ISAF(32R6)
+#define INSN_UPTO64 INSN_UPTO5 | ISAF(64) | ISAF(32)
+#define INSN_UPTO64R2 INSN_UPTO64 | ISAF(64R2) | ISAF(32R2)
+#define INSN_UPTO64R3 INSN_UPTO64R2 | ISAF(64R3) | ISAF(32R3)
+#define INSN_UPTO64R5 INSN_UPTO64R3 | ISAF(64R5) | ISAF(32R5)
+#define INSN_UPTO64R6 INSN_UPTO64R5 | ISAF(64R6) | ISAF(32R6)
+
+/* The same information in table form: bit INSN_ISA<X> - 1 of index
+ INSN_UPTO<Y> - 1 is set if ISA Y includes ISA X. */
+static const unsigned int mips_isa_table[] = {
+ INSN_UPTO1,
+ INSN_UPTO2,
+ INSN_UPTO3,
+ INSN_UPTO4,
+ INSN_UPTO5,
+ INSN_UPTO32,
+ INSN_UPTO32R2,
+ INSN_UPTO32R3,
+ INSN_UPTO32R5,
+ INSN_UPTO32R6,
+ INSN_UPTO64,
+ INSN_UPTO64R2,
+ INSN_UPTO64R3,
+ INSN_UPTO64R5,
+ INSN_UPTO64R6
+};
+#undef ISAF
/* Masks used for Chip specific instructions. */
#define INSN_CHIP_MASK 0xc3ff0f20
@@ -724,18 +1196,10 @@ static const unsigned int mips_isa_table[] =
#define INSN_OCTEON 0x00000800
#define INSN_OCTEONP 0x00000200
#define INSN_OCTEON2 0x00000100
+#define INSN_OCTEON3 0x00000040
-/* Masks used for MIPS-defined ASEs. */
-#define INSN_ASE_MASK 0x3c00f010
-
-/* DSP ASE */
-#define INSN_DSP 0x00001000
-#define INSN_DSP64 0x00002000
-
-/* 0x00004000 is unused. */
-
-/* MIPS-3D ASE */
-#define INSN_MIPS3D 0x00008000
+/* MIPS R5900 instruction */
+#define INSN_5900 0x00004000
/* MIPS R4650 instruction. */
#define INSN_4650 0x00010000
@@ -758,14 +1222,6 @@ static const unsigned int mips_isa_table[] =
/* NEC VR5500 instruction. */
#define INSN_5500 0x02000000
-/* MDMX ASE */
-#define INSN_MDMX 0x04000000
-/* MT ASE */
-#define INSN_MT 0x08000000
-/* SmartMIPS ASE */
-#define INSN_SMARTMIPS 0x10000000
-/* DSP R2 ASE */
-#define INSN_DSPR2 0x20000000
/* ST Microelectronics Loongson 2E. */
#define INSN_LOONGSON_2E 0x40000000
/* ST Microelectronics Loongson 2F. */
@@ -773,10 +1229,33 @@ static const unsigned int mips_isa_table[] =
/* Loongson 3A. */
#define INSN_LOONGSON_3A 0x00000400
/* RMI Xlr instruction */
-#define INSN_XLR 0x00000020
+#define INSN_XLR 0x00000020
+/* DSP ASE */
+#define ASE_DSP 0x00000001
+#define ASE_DSP64 0x00000002
+/* DSP R2 ASE */
+#define ASE_DSPR2 0x00000004
+/* Enhanced VA Scheme */
+#define ASE_EVA 0x00000008
/* MCU (MicroController) ASE */
-#define INSN_MCU 0x00000010
+#define ASE_MCU 0x00000010
+/* MDMX ASE */
+#define ASE_MDMX 0x00000020
+/* MIPS-3D ASE */
+#define ASE_MIPS3D 0x00000040
+/* MT ASE */
+#define ASE_MT 0x00000080
+/* SmartMIPS ASE */
+#define ASE_SMARTMIPS 0x00000100
+/* Virtualization ASE */
+#define ASE_VIRT 0x00000200
+#define ASE_VIRT64 0x00000400
+/* MSA Extension */
+#define ASE_MSA 0x00000800
+#define ASE_MSA64 0x00001000
+/* eXtended Physical Address (XPA) Extension. */
+#define ASE_XPA 0x00002000
/* MIPS ISA defines, use instead of hardcoding ISA level. */
@@ -791,8 +1270,14 @@ static const unsigned int mips_isa_table[] =
#define ISA_MIPS64 INSN_ISA64
#define ISA_MIPS32R2 INSN_ISA32R2
+#define ISA_MIPS32R3 INSN_ISA32R3
+#define ISA_MIPS32R5 INSN_ISA32R5
#define ISA_MIPS64R2 INSN_ISA64R2
+#define ISA_MIPS64R3 INSN_ISA64R3
+#define ISA_MIPS64R5 INSN_ISA64R5
+#define ISA_MIPS32R6 INSN_ISA32R6
+#define ISA_MIPS64R6 INSN_ISA64R6
/* CPU defines, use instead of hardcoding processor number. Keep this
in sync with bfd/archures.c in order for machine selection to work. */
@@ -811,6 +1296,7 @@ static const unsigned int mips_isa_table[] =
#define CPU_R5000 5000
#define CPU_VR5400 5400
#define CPU_VR5500 5500
+#define CPU_R5900 5900
#define CPU_R6000 6000
#define CPU_RM7000 7000
#define CPU_R8000 8000
@@ -822,9 +1308,15 @@ static const unsigned int mips_isa_table[] =
#define CPU_MIPS16 16
#define CPU_MIPS32 32
#define CPU_MIPS32R2 33
+#define CPU_MIPS32R3 34
+#define CPU_MIPS32R5 36
+#define CPU_MIPS32R6 37
#define CPU_MIPS5 5
#define CPU_MIPS64 64
#define CPU_MIPS64R2 65
+#define CPU_MIPS64R3 66
+#define CPU_MIPS64R5 68
+#define CPU_MIPS64R6 69
#define CPU_SB1 12310201 /* octal 'SB', 01. */
#define CPU_LOONGSON_2E 3001
#define CPU_LOONGSON_2F 3002
@@ -832,6 +1324,7 @@ static const unsigned int mips_isa_table[] =
#define CPU_OCTEON 6501
#define CPU_OCTEONP 6601
#define CPU_OCTEON2 6502
+#define CPU_OCTEON3 6503
#define CPU_XLR 887682 /* decimal 'XLR' */
/* Return true if the given CPU is included in INSN_* mask MASK. */
@@ -876,6 +1369,9 @@ cpu_is_member (int cpu, unsigned int mask)
case CPU_VR5500:
return (mask & INSN_5500) != 0;
+ case CPU_R5900:
+ return (mask & INSN_5900) != 0;
+
case CPU_LOONGSON_2E:
return (mask & INSN_LOONGSON_2E) != 0;
@@ -894,9 +1390,19 @@ cpu_is_member (int cpu, unsigned int mask)
case CPU_OCTEON2:
return (mask & INSN_OCTEON2) != 0;
+ case CPU_OCTEON3:
+ return (mask & INSN_OCTEON3) != 0;
+
case CPU_XLR:
return (mask & INSN_XLR) != 0;
+ case CPU_MIPS32R6:
+ return (mask & INSN_ISA_MASK) == INSN_ISA32R6;
+
+ case CPU_MIPS64R6:
+ return ((mask & INSN_ISA_MASK) == INSN_ISA32R6)
+ || ((mask & INSN_ISA_MASK) == INSN_ISA64R6);
+
default:
return FALSE;
}
@@ -909,7 +1415,7 @@ cpu_is_member (int cpu, unsigned int mask)
if instruction INSN is available to the given ISA and CPU. */
static inline bfd_boolean
-opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
+opcode_is_member (const struct mips_opcode *insn, int isa, int ase, int cpu)
{
if (!cpu_is_member (cpu, insn->exclusions))
{
@@ -921,7 +1427,7 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
return TRUE;
/* Test for ASE compatibility. */
- if (((isa & ~INSN_ISA_MASK) & (insn->membership & ~INSN_ISA_MASK)) != 0)
+ if ((ase & insn->ase) != 0)
return TRUE;
/* Test for processor-specific extensions. */
@@ -934,8 +1440,8 @@ opcode_is_member (const struct mips_opcode *insn, int isa, int cpu)
/* This is a list of macro expanded instructions.
_I appended means immediate
- _A appended means address
- _AB appended means address with base register
+ _A appended means target address of a jump
+ _AB appended means address with (possibly zero) base register
_D appended means 64 bit floating point constant
_S appended means 32 bit floating point constant. */
@@ -943,12 +1449,10 @@ enum
{
M_ABS,
M_ACLR_AB,
- M_ACLR_OB,
M_ADD_I,
M_ADDU_I,
M_AND_I,
M_ASET_AB,
- M_ASET_OB,
M_BALIGN,
M_BC1FL,
M_BC1TL,
@@ -1005,7 +1509,7 @@ enum
M_BNE_I,
M_BNEL_I,
M_CACHE_AB,
- M_CACHE_OB,
+ M_CACHEE_AB,
M_DABS,
M_DADD_I,
M_DADDU_I,
@@ -1013,8 +1517,6 @@ enum
M_DDIV_3I,
M_DDIVU_3,
M_DDIVU_3I,
- M_DEXT,
- M_DINS,
M_DIV_3,
M_DIV_3I,
M_DIVU_3,
@@ -1046,72 +1548,57 @@ enum
M_JALS_1,
M_JALS_2,
M_JALS_A,
- M_L_DOB,
+ M_JRADDIUSP,
+ M_JRC,
M_L_DAB,
M_LA_AB,
- M_LB_A,
M_LB_AB,
- M_LBU_A,
+ M_LBE_AB,
M_LBU_AB,
+ M_LBUE_AB,
M_LCA_AB,
- M_LD_A,
- M_LD_OB,
M_LD_AB,
M_LDC1_AB,
M_LDC2_AB,
- M_LDC2_OB,
+ M_LQC2_AB,
M_LDC3_AB,
M_LDL_AB,
- M_LDL_OB,
M_LDM_AB,
- M_LDM_OB,
M_LDP_AB,
- M_LDP_OB,
M_LDR_AB,
- M_LDR_OB,
- M_LH_A,
M_LH_AB,
- M_LHU_A,
+ M_LHE_AB,
M_LHU_AB,
+ M_LHUE_AB,
M_LI,
M_LI_D,
M_LI_DD,
M_LI_S,
M_LI_SS,
M_LL_AB,
- M_LL_OB,
M_LLD_AB,
- M_LLD_OB,
- M_LS_A,
- M_LW_A,
+ M_LLE_AB,
+ M_LQ_AB,
M_LW_AB,
- M_LWC0_A,
+ M_LWE_AB,
M_LWC0_AB,
- M_LWC1_A,
M_LWC1_AB,
- M_LWC2_A,
M_LWC2_AB,
- M_LWC2_OB,
- M_LWC3_A,
M_LWC3_AB,
- M_LWL_A,
M_LWL_AB,
- M_LWL_OB,
+ M_LWLE_AB,
M_LWM_AB,
- M_LWM_OB,
M_LWP_AB,
- M_LWP_OB,
- M_LWR_A,
M_LWR_AB,
- M_LWR_OB,
+ M_LWRE_AB,
M_LWU_AB,
- M_LWU_OB,
M_MSGSND,
M_MSGLD,
M_MSGLD_T,
M_MSGWAIT,
M_MSGWAIT_T,
M_MOVE,
+ M_MOVEP,
M_MUL,
M_MUL_I,
M_MULO,
@@ -1121,7 +1608,7 @@ enum
M_NOR_I,
M_OR_I,
M_PREF_AB,
- M_PREF_OB,
+ M_PREFE_AB,
M_REM_3,
M_REM_3I,
M_REMU_3,
@@ -1135,32 +1622,22 @@ enum
M_DROR_I,
M_ROR_I,
M_S_DA,
- M_S_DOB,
M_S_DAB,
M_S_S,
M_SAA_AB,
- M_SAA_OB,
M_SAAD_AB,
- M_SAAD_OB,
M_SC_AB,
- M_SC_OB,
M_SCD_AB,
- M_SCD_OB,
- M_SD_A,
- M_SD_OB,
+ M_SCE_AB,
M_SD_AB,
M_SDC1_AB,
M_SDC2_AB,
- M_SDC2_OB,
+ M_SQC2_AB,
M_SDC3_AB,
M_SDL_AB,
- M_SDL_OB,
M_SDM_AB,
- M_SDM_OB,
M_SDP_AB,
- M_SDP_OB,
M_SDR_AB,
- M_SDR_OB,
M_SEQ,
M_SEQ_I,
M_SGE,
@@ -1179,31 +1656,23 @@ enum
M_SLTU_I,
M_SNE,
M_SNE_I,
- M_SB_A,
M_SB_AB,
- M_SH_A,
+ M_SBE_AB,
M_SH_AB,
- M_SW_A,
+ M_SHE_AB,
+ M_SQ_AB,
M_SW_AB,
- M_SWC0_A,
+ M_SWE_AB,
M_SWC0_AB,
- M_SWC1_A,
M_SWC1_AB,
- M_SWC2_A,
M_SWC2_AB,
- M_SWC2_OB,
- M_SWC3_A,
M_SWC3_AB,
- M_SWL_A,
M_SWL_AB,
- M_SWL_OB,
+ M_SWLE_AB,
M_SWM_AB,
- M_SWM_OB,
M_SWP_AB,
- M_SWP_OB,
- M_SWR_A,
M_SWR_AB,
- M_SWR_OB,
+ M_SWRE_AB,
M_SUB_I,
M_SUBU_I,
M_SUBU_I_2,
@@ -1215,20 +1684,13 @@ enum
M_TNE_I,
M_TRUNCWD,
M_TRUNCWS,
- M_ULD,
- M_ULD_A,
- M_ULH,
- M_ULH_A,
- M_ULHU,
- M_ULHU_A,
- M_ULW,
- M_ULW_A,
- M_USH,
- M_USH_A,
- M_USW,
- M_USW_A,
- M_USD,
- M_USD_A,
+ M_ULD_AB,
+ M_ULH_AB,
+ M_ULHU_AB,
+ M_ULW_AB,
+ M_USH_AB,
+ M_USW_AB,
+ M_USD_AB,
M_XOR_I,
M_COP0,
M_COP1,
@@ -1248,6 +1710,8 @@ enum
Many instructions are short hand for other instructions (i.e., The
jal <register> instruction is short for jalr <register>). */
+extern const struct mips_operand mips_vu0_channel_mask;
+extern const struct mips_operand *decode_mips_operand (const char *);
extern const struct mips_opcode mips_builtin_opcodes[];
extern const int bfd_mips_num_builtin_opcodes;
extern struct mips_opcode *mips_opcodes;
@@ -1333,10 +1797,13 @@ extern int bfd_mips_num_opcodes;
"Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
"6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
"a" 26 bit jump address
+ "i" likewise, but flips bit 0
"e" 11 bit extension value
"l" register list for entry instruction
"L" register list for exit instruction
+ "I" an immediate value used for macros
+
The remaining codes may be extended. Except as otherwise noted,
the full extended operand is a 16 bit signed value.
"<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
@@ -1369,44 +1836,6 @@ extern int bfd_mips_num_opcodes;
#define MIPS16_ALL_ARGS 0xe
#define MIPS16_ALL_STATICS 0xb
-/* For the mips16, we use the same opcode table format and a few of
- the same flags. However, most of the flags are different. */
-
-/* Modifies the register in MIPS16OP_*_RX. */
-#define MIPS16_INSN_WRITE_X 0x00000001
-/* Modifies the register in MIPS16OP_*_RY. */
-#define MIPS16_INSN_WRITE_Y 0x00000002
-/* Modifies the register in MIPS16OP_*_RZ. */
-#define MIPS16_INSN_WRITE_Z 0x00000004
-/* Modifies the T ($24) register. */
-#define MIPS16_INSN_WRITE_T 0x00000008
-/* Modifies the SP ($29) register. */
-#define MIPS16_INSN_WRITE_SP 0x00000010
-/* Modifies the RA ($31) register. */
-#define MIPS16_INSN_WRITE_31 0x00000020
-/* Modifies the general purpose register in MIPS16OP_*_REG32R. */
-#define MIPS16_INSN_WRITE_GPR_Y 0x00000040
-/* Reads the register in MIPS16OP_*_RX. */
-#define MIPS16_INSN_READ_X 0x00000080
-/* Reads the register in MIPS16OP_*_RY. */
-#define MIPS16_INSN_READ_Y 0x00000100
-/* Reads the register in MIPS16OP_*_MOVE32Z. */
-#define MIPS16_INSN_READ_Z 0x00000200
-/* Reads the T ($24) register. */
-#define MIPS16_INSN_READ_T 0x00000400
-/* Reads the SP ($29) register. */
-#define MIPS16_INSN_READ_SP 0x00000800
-/* Reads the RA ($31) register. */
-#define MIPS16_INSN_READ_31 0x00001000
-/* Reads the program counter. */
-#define MIPS16_INSN_READ_PC 0x00002000
-/* Reads the general purpose register in MIPS16OP_*_REGR32. */
-#define MIPS16_INSN_READ_GPR_X 0x00004000
-/* Is an unconditional branch insn. */
-#define MIPS16_INSN_UNCOND_BRANCH 0x00008000
-/* Is a conditional branch insn. */
-#define MIPS16_INSN_COND_BRANCH 0x00010000
-
/* The following flags have the same value for the mips16 opcode
table:
@@ -1423,6 +1852,7 @@ extern int bfd_mips_num_opcodes;
FP_D (never used)
*/
+extern const struct mips_operand *decode_mips16_operand (char, bfd_boolean);
extern const struct mips_opcode mips16_opcodes[];
extern const int bfd_mips16_num_opcodes;
@@ -1503,8 +1933,6 @@ extern const int bfd_mips16_num_opcodes;
#define MICROMIPSOP_SH_MG 0
#define MICROMIPSOP_MASK_MH 0x7
#define MICROMIPSOP_SH_MH 7
-#define MICROMIPSOP_MASK_MI 0x7
-#define MICROMIPSOP_SH_MI 7
#define MICROMIPSOP_MASK_MJ 0x1f
#define MICROMIPSOP_SH_MJ 0
#define MICROMIPSOP_MASK_ML 0x7
@@ -1624,6 +2052,10 @@ extern const int bfd_mips16_num_opcodes;
#define MICROMIPSOP_SH_FZ 0
#define MICROMIPSOP_MASK_FZ 0
+/* microMIPS Enhanced VA Scheme */
+#define MICROMIPSOP_SH_EVAOFFSET 0
+#define MICROMIPSOP_MASK_EVAOFFSET 0x1ff
+
/* These are the characters which may appears in the args field of a microMIPS
instruction. They appear in the order in which the fields appear
when the instruction is used. Commas and parentheses in the args
@@ -1640,9 +2072,7 @@ extern const int bfd_mips16_num_opcodes;
The same register used as both source and target.
"mf" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MF) at bit 3
"mg" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_MG) at bit 0
- "mh" MIPS registers 4, 5, 6 (MICROMIPSOP_*_MH) at bit 7
- "mi" MIPS registers 5, 6, 7, 21, 22 (MICROMIPSOP_*_MI) at bit 7
- ("mh" and "mi" form a valid 3-bit register pair)
+ "mh" 3-bit MIPS register pair (MICROMIPSOP_*_MH) at bit 7
"mj" 5-bit MIPS registers (MICROMIPSOP_*_MJ) at bit 0
"ml" 3-bit MIPS registers 2-7, 16, 17 (MICROMIPSOP_*_ML) at bit 4
"mm" 3-bit MIPS registers 0, 2, 3, 16-20 (MICROMIPSOP_*_MM) at bit 1
@@ -1683,7 +2113,7 @@ extern const int bfd_mips16_num_opcodes;
others too).
"." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10)
- "1" 5-bit sync type (MICROMIPSOP_*_SHAMT)
+ "1" 5-bit sync type (MICROMIPSOP_*_STYPE)
"<" 5-bit shift amount (MICROMIPSOP_*_SHAMT)
">" shift amount between 32 and 63, stored after subtracting 32
(MICROMIPSOP_*_SHAMT)
@@ -1691,6 +2121,7 @@ extern const int bfd_mips16_num_opcodes;
"|" 4-bit trap code (MICROMIPSOP_*_TRAP)
"~" 12-bit signed offset (MICROMIPSOP_*_OFFSET12)
"a" 26-bit target address (MICROMIPSOP_*_TARGET)
+ "+i" likewise, but flips bit 0
"b" 5-bit base register (MICROMIPSOP_*_RS)
"c" 10-bit higher breakpoint code (MICROMIPSOP_*_CODE)
"d" 5-bit destination register specifier (MICROMIPSOP_*_RD)
@@ -1713,7 +2144,6 @@ extern const int bfd_mips16_num_opcodes;
"y" 5-bit source 3 register for ALNV.PS (MICROMIPSOP_*_RS3)
"z" must be zero register
"C" 23-bit coprocessor function code (MICROMIPSOP_*_COPZ)
- "B" 10-bit syscall/wait function code (MICROMIPSOP_*_CODE10)
"K" 5-bit Hardware Register (RDHWR instruction) (MICROMIPSOP_*_RS)
"+A" 5-bit INS/EXT/DINS/DEXT/DINSM/DEXTM position, which becomes
@@ -1738,6 +2168,8 @@ extern const int bfd_mips16_num_opcodes;
"+H" 5-bit DEXTU size, which becomes MSBD (MICROMIPSOP_*_EXTMSBD).
Requires that "+A" or "+E" occur first to set position.
Enforces: 32 < (pos+size) <= 64.
+ "+J" 10-bit SYSCALL/WAIT/SDBBP/HYPCALL function code
+ (MICROMIPSOP_*_CODE10)
PC-relative addition (ADDIUPC) instruction:
"mQ" 23-bit offset (-4194304 .. 4194303) << 2 (MICROMIPSOP_*_IMMQ)
@@ -1755,15 +2187,12 @@ extern const int bfd_mips16_num_opcodes;
Coprocessor instructions:
"E" 5-bit target register (MICROMIPSOP_*_RT)
- "G" 5-bit destination register (MICROMIPSOP_*_RD)
+ "G" 5-bit source register (MICROMIPSOP_*_RS)
"H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL)
- "+D" combined destination register ("G") and sel ("H") for CP0 ops,
- for pretty-printing in disassembly only
Macro instructions:
"A" general 32 bit expression
"I" 32-bit immediate (value placed in imm_expr).
- "+I" 32-bit immediate (value placed in imm2_expr).
"F" 64-bit floating point constant in .rdata
"L" 64-bit floating point constant in .lit8
"f" 32-bit floating point constant
@@ -1781,6 +2210,36 @@ extern const int bfd_mips16_num_opcodes;
"@" 10-bit signed immediate (MICROMIPSOP_*_IMM10)
"^" 5-bit unsigned immediate (MICROMIPSOP_*_RD)
+ microMIPS Enhanced VA Scheme:
+ "+j" 9-bit signed offset in bit 0 (OP_*_EVAOFFSET)
+
+ MSA Extension:
+ "+d" 5-bit MSA register (FD)
+ "+e" 5-bit MSA register (FS)
+ "+h" 5-bit MSA register (FT)
+ "+k" 5-bit GPR at bit 6
+ "+l" 5-bit MSA control register at bit 6
+ "+n" 5-bit MSA control register at bit 11
+ "+o" 4-bit vector element index at bit 16
+ "+u" 3-bit vector element index at bit 16
+ "+v" 2-bit vector element index at bit 16
+ "+w" 1-bit vector element index at bit 16
+ "+x" 5-bit shift amount at bit 16
+ "+T" (-512 .. 511) << 0 at bit 16
+ "+U" (-512 .. 511) << 1 at bit 16
+ "+V" (-512 .. 511) << 2 at bit 16
+ "+W" (-512 .. 511) << 3 at bit 16
+ "+~" 2 bit LSA/DLSA shift amount from 1 to 4 at bit 6
+ "+!" 3 bit unsigned bit position at bit 16
+ "+@" 4 bit unsigned bit position at bit 16
+ "+#" 6 bit unsigned bit position at bit 16
+ "+$" 5 bit unsigned immediate at bit 16
+ "+%" 5 bit signed immediate at bit 16
+ "+^" 10 bit signed immediate at bit 11
+ "+&" 0 vector element index
+ "+*" 5-bit register vector element index at bit 16
+ "+|" 8-bit mask at bit 16
+
Other:
"()" parens surrounding optional value
"," separates operands
@@ -1789,16 +2248,16 @@ extern const int bfd_mips16_num_opcodes;
Characters used so far, for quick reference when adding more:
"12345678 0"
- "<>(),+.@\^|~"
+ "<>(),+-.@\^|~"
"ABCDEFGHI KLMN RST V "
"abcd f hijklmnopqrstuvw yz"
Extension character sequences used so far ("+" followed by the
following), for quick reference when adding more:
""
- ""
- "ABCDEFGHI"
- ""
+ "~!@#$%^&*|"
+ "ABCEFGHJTUVW"
+ "dehijklnouvwx"
Extension character sequences used so far ("m" followed by the
following), for quick reference when adding more:
@@ -1806,8 +2265,15 @@ extern const int bfd_mips16_num_opcodes;
""
" BCDEFGHIJ LMNOPQ U WXYZ"
" bcdefghij lmn pq st xyz"
+
+ Extension character sequences used so far ("-" followed by the
+ following), for quick reference when adding more:
+ ""
+ ""
+ <none so far>
*/
+extern const struct mips_operand *decode_micromips_operand (const char *);
extern const struct mips_opcode micromips_opcodes[];
extern const int bfd_micromips_num_opcodes;
diff --git a/external/gpl3/binutils/dist/include/opcode/or32.h b/external/gpl3/binutils/dist/include/opcode/or32.h
deleted file mode 100644
index 153d91ec42f..00000000000
--- a/external/gpl3/binutils/dist/include/opcode/or32.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/* Table of opcodes for the OpenRISC 1000 ISA.
- Copyright 2002, 2003, 2010 Free Software Foundation, Inc.
- Contributed by Damjan Lampret (lampret@opencores.org).
-
- This file is part of or1k_gen_isa, or1ksim, GDB and GAS.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 3 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
- MA 02110-1301, USA. */
-
-/* We treat all letters the same in encode/decode routines so
- we need to assign some characteristics to them like signess etc. */
-
-#ifndef OR32_H_ISA
-#define OR32_H_ISA
-
-#define NUM_UNSIGNED (0)
-#define NUM_SIGNED (1)
-
-#define MAX_GPRS 32
-#define PAGE_SIZE 4096
-#undef __HALF_WORD_INSN__
-
-#define OPERAND_DELIM (',')
-
-#define OR32_IF_DELAY (1)
-#define OR32_W_FLAG (2)
-#define OR32_R_FLAG (4)
-
-struct or32_letter
-{
- char letter;
- int sign;
- /* int reloc; relocation per letter ?? */
-};
-
-/* Main instruction specification array. */
-struct or32_opcode
-{
- /* Name of the instruction. */
- char *name;
-
- /* A string of characters which describe the operands.
- Valid characters are:
- ,() Itself. Characters appears in the assembly code.
- rA Register operand.
- rB Register operand.
- rD Register operand.
- I An immediate operand, range -32768 to 32767.
- J An immediate operand, range . (unused)
- K An immediate operand, range 0 to 65535.
- L An immediate operand, range 0 to 63.
- M An immediate operand, range . (unused)
- N An immediate operand, range -33554432 to 33554431.
- O An immediate operand, range . (unused). */
- char *args;
-
- /* Opcode and operand encoding. */
- char *encoding;
- void (*exec) (void);
- unsigned int flags;
-};
-
-#define OPTYPE_LAST (0x80000000)
-#define OPTYPE_OP (0x40000000)
-#define OPTYPE_REG (0x20000000)
-#define OPTYPE_SIG (0x10000000)
-#define OPTYPE_DIS (0x08000000)
-#define OPTYPE_DST (0x04000000)
-#define OPTYPE_SBIT (0x00001F00)
-#define OPTYPE_SHR (0x0000001F)
-#define OPTYPE_SBIT_SHR (8)
-
-/* MM: Data how to decode operands. */
-extern struct insn_op_struct
-{
- unsigned long type;
- unsigned long data;
-} **op_start;
-
-#ifdef HAS_EXECUTION
-extern void l_invalid (void);
-extern void l_sfne (void);
-extern void l_bf (void);
-extern void l_add (void);
-extern void l_sw (void);
-extern void l_sb (void);
-extern void l_sh (void);
-extern void l_lwz (void);
-extern void l_lbs (void);
-extern void l_lbz (void);
-extern void l_lhs (void);
-extern void l_lhz (void);
-extern void l_movhi (void);
-extern void l_and (void);
-extern void l_or (void);
-extern void l_xor (void);
-extern void l_sub (void);
-extern void l_mul (void);
-extern void l_div (void);
-extern void l_divu (void);
-extern void l_sll (void);
-extern void l_sra (void);
-extern void l_srl (void);
-extern void l_j (void);
-extern void l_jal (void);
-extern void l_jalr (void);
-extern void l_jr (void);
-extern void l_rfe (void);
-extern void l_nop (void);
-extern void l_bnf (void);
-extern void l_sfeq (void);
-extern void l_sfgts (void);
-extern void l_sfges (void);
-extern void l_sflts (void);
-extern void l_sfles (void);
-extern void l_sfgtu (void);
-extern void l_sfgeu (void);
-extern void l_sfltu (void);
-extern void l_sfleu (void);
-extern void l_mtspr (void);
-extern void l_mfspr (void);
-extern void l_sys (void);
-extern void l_trap (void); /* CZ 21/06/01. */
-extern void l_macrc (void);
-extern void l_mac (void);
-extern void l_msb (void);
-extern void l_invalid (void);
-extern void l_cust1 (void);
-extern void l_cust2 (void);
-extern void l_cust3 (void);
-extern void l_cust4 (void);
-#endif
-extern void l_none (void);
-
-extern const struct or32_letter or32_letters[];
-
-extern const struct or32_opcode or32_opcodes[];
-
-extern const unsigned int or32_num_opcodes;
-
-/* Calculates instruction length in bytes. Always 4 for OR32. */
-extern int insn_len (int);
-
-/* Is individual insn's operand signed or unsigned? */
-extern int letter_signed (char);
-
-/* Number of letters in the individual lettered operand. */
-extern int letter_range (char);
-
-/* MM: Returns index of given instruction name. */
-extern int insn_index (char *);
-
-/* MM: Returns instruction name from index. */
-extern const char *insn_name (int);
-
-/* MM: Constructs new FSM, based on or32_opcodes. */
-extern void build_automata (void);
-
-/* MM: Destructs FSM. */
-extern void destruct_automata (void);
-
-/* MM: Decodes instruction using FSM. Call build_automata first. */
-extern int insn_decode (unsigned int);
-
-/* Disassemble one instruction from insn to disassemble.
- Return the size of the instruction. */
-int disassemble_insn (unsigned long);
-
-#endif
diff --git a/external/gpl3/binutils/dist/include/opcode/ppc.h b/external/gpl3/binutils/dist/include/opcode/ppc.h
index e57b118b02e..44d2d6cc11a 100644
--- a/external/gpl3/binutils/dist/include/opcode/ppc.h
+++ b/external/gpl3/binutils/dist/include/opcode/ppc.h
@@ -1,6 +1,5 @@
/* ppc.h -- Header file for PowerPC opcode table
- Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
- 2007, 2008, 2009, 2010, 2012 Free Software Foundation, Inc.
+ Copyright (C) 1994-2015 Free Software Foundation, Inc.
Written by Ian Lance Taylor, Cygnus Support
This file is part of GDB, GAS, and the GNU binutils.
@@ -188,6 +187,29 @@ extern const int vle_num_opcodes;
/* Opcode which is supported by the VLE extension. */
#define PPC_OPCODE_VLE 0x1000000000ull
+/* Opcode is only supported by Power8 architecture. */
+#define PPC_OPCODE_POWER8 0x2000000000ull
+
+/* Opcode which is supported by the Hardware Transactional Memory extension. */
+/* Currently, this is the same as the POWER8 mask. If another cpu comes out
+ that isn't a superset of POWER8, we can define this to its own mask. */
+#define PPC_OPCODE_HTM PPC_OPCODE_POWER8
+
+/* Opcode is supported by ppc750cl. */
+#define PPC_OPCODE_750 0x4000000000ull
+
+/* Opcode is supported by ppc7450. */
+#define PPC_OPCODE_7450 0x8000000000ull
+
+/* Opcode is supported by ppc821/850/860. */
+#define PPC_OPCODE_860 0x10000000000ull
+
+/* Opcode is only supported by Power9 architecture. */
+#define PPC_OPCODE_POWER9 0x20000000000ull
+
+/* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08. */
+#define PPC_OPCODE_VSX3 0x40000000000ull
+
/* A macro to extract the major opcode from an instruction. */
#define PPC_OP(i) (((i) >> 26) & 0x3f)
@@ -270,7 +292,7 @@ extern const unsigned int num_powerpc_operands;
/* Use with the shift field of a struct powerpc_operand to indicate
that BITM and SHIFT cannot be used to determine where the operand
goes in the insn. */
-#define PPC_OPSHIFT_INV (-1 << 31)
+#define PPC_OPSHIFT_INV (-1U << 31)
/* Values defined for the flags field of a struct powerpc_operand. */
@@ -373,6 +395,11 @@ extern const unsigned int num_powerpc_operands;
/* This is a CR FIELD that does not use symbolic names. */
#define PPC_OPERAND_CR_REG (0x200000)
+
+/* This flag is only used with PPC_OPERAND_OPTIONAL. If this operand
+ is omitted, then the value it should use for the operand is stored
+ in the SHIFT field of the immediatly following operand field. */
+#define PPC_OPERAND_OPTIONAL_VALUE (0x400000)
/* The POWER and PowerPC assemblers use a few macros. We keep them
with the operands table for simplicity. The macro table is an
@@ -402,4 +429,12 @@ extern const int powerpc_num_macros;
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
+static inline long
+ppc_optional_operand_value (const struct powerpc_operand *operand)
+{
+ if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)
+ return (operand+1)->shift;
+ return 0;
+}
+
#endif /* PPC_H */