diff options
| author | skrll <skrll@NetBSD.org> | 2006-02-02 20:58:06 +0000 |
|---|---|---|
| committer | skrll <skrll@NetBSD.org> | 2006-02-02 20:58:06 +0000 |
| commit | 8d2c6a4e34b1fbb538663dee24b3dce5a6ad7ce8 (patch) | |
| tree | 01a760df00b921200616456eed856334b4fdd092 /gnu/dist/binutils/include/opcode | |
| parent | 27523fbf84c1ee6539d56f021f9ed5f7f9a0dd70 (diff) | |
Import binutils 2.16.1.
Diffstat (limited to 'gnu/dist/binutils/include/opcode')
20 files changed, 2530 insertions, 875 deletions
diff --git a/gnu/dist/binutils/include/opcode/ChangeLog b/gnu/dist/binutils/include/opcode/ChangeLog index 6c50775ea1c..2152ae57e70 100644 --- a/gnu/dist/binutils/include/opcode/ChangeLog +++ b/gnu/dist/binutils/include/opcode/ChangeLog @@ -1,13 +1,187 @@ -2004-04-08 Alan Modra <amodra@bigpond.net.au> +2005-03-15 Jan Beulich <jbeulich@novell.com> - Apply from mainline. - 2004-03-12 Jakub Jelinek <jakub@redhat.com> - * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. + * i386.h (i386_optab): Add rdtscp. + +2005-02-09 Jan Beulich <jbeulich@novell.com> + + PR gas/707 + * i386.h (i386_optab): Add x_Suf to fbld and fbstp. Add w_Suf and + FloatMF to fldcw, fstcw, fnstcw, and the memory formas of fstsw and + fnstsw. + +2005-01-25 Alexandre Oliva <aoliva@redhat.com> + + 2004-11-10 Alexandre Oliva <aoliva@redhat.com> + * cgen.h (enum cgen_parse_operand_type): Add + CGEN_PARSE_OPERAND_SYMBOLIC. + +2005-01-21 Fred Fish <fnf@specifixinc.com> + + * mips.h: Change INSN_ALIAS to INSN2_ALIAS. + Change INSN_WRITE_MDMX_ACC to INSN2_WRITE_MDMX_ACC. + Change INSN_READ_MDMX_ACC to INSN2_READ_MDMX_ACC. + +2005-01-19 Fred Fish <fnf@specifixinc.com> + + * mips.h (struct mips_opcode): Add new pinfo2 member. + (INSN_ALIAS): New define for opcode table entries that are + specific instances of another entry, such as 'move' for an 'or' + with a zero operand. + (INSN_READ_MDMX_ACC): Redefine from 0 to 0x2. + (INSN_WRITE_MDMX_ACC): Redefine from 0 to 0x4. + +2004-12-09 Ian Lance Taylor <ian@wasabisystems.com> + + * mips.h (CPU_RM9000): Define. + (OPCODE_IS_MEMBER): Handle CPU_RM9000. + +2004-11-25 Jan Beulich <jbeulich@novell.com> + + * i386.h: CpuNo64 mov can't reasonably have a 'q' suffix. Moves + to/from test registers are illegal in 64-bit mode. Add missing + NoRex64 to sidt. fxsave/fxrstor now allow for a 'q' suffix + (previously one had to explicitly encode a rex64 prefix). Re-enable + lahf/sahf in 64-bit mode as at least some Athlon64/Opteron steppings + support it there. Add cmpxchg16b as per Intel's 64-bit documentation. + +2004-11-23 Jan Beulich <jbeulich@novell.com> + + * i386.h (i386_optab): paddq and psubq, even in their MMX form, are + available only with SSE2. Change the MMX additions introduced by SSE + and 3DNow!A to CpuMMX2 (rather than CpuMMX). Indicate the 3DNow!A + instructions by their now designated identifier (since combining i686 + and 3DNow! does not really imply 3DNow!A). + +2004-11-19 Alan Modra <amodra@bigpond.net.au> + + * msp430.h (struct rcodes_s, MSP430_RLC, msp430_rcodes, + struct hcodes_s, msp430_hcodes): Move to gas/config/tc-msp430.c. + +2004-11-08 Inderpreet Singh <inderpreetb@nioda.hcltech.com> + Vineet Sharma <vineets@noida.hcltech.com> + + * maxq.h: New file: Disassembly information for the maxq port. + +2004-11-05 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Put back "movzb". + +2004-11-04 Hans-Peter Nilsson <hp@axis.com> + + * cris.h (enum cris_insn_version_usage): Tweak formatting and + comments. Remove member cris_ver_sim. Add members + cris_ver_sim_v0_10, cris_ver_v0_10, cris_ver_v3_10, + cris_ver_v8_10, cris_ver_v10, cris_ver_v10p. + (struct cris_support_reg, struct cris_cond15): New types. + (cris_conds15): Declare. + (JUMP_PC_INCR_OPCODE_V32, BA_DWORD_OPCODE, NOP_OPCODE_COMMON) + (NOP_OPCODE_ZBITS_COMMON, LAPC_DWORD_OPCODE, LAPC_DWORD_Z_BITS) + (NOP_OPCODE_V32, NOP_Z_BITS_V32): New macros. + (NOP_Z_BITS): Define in terms of NOP_OPCODE. + (cris_imm_oprnd_size_type): New members SIZE_FIELD_SIGNED and + SIZE_FIELD_UNSIGNED. + +2004-11-04 Jan Beulich <jbeulich@novell.com> + + * i386.h (sldx_Suf): Remove. + (FP, l_FP, sl_FP, x_FP): Don't imply IgnoreSize. + (q_FP): Define, implying no REX64. + (x_FP, sl_FP): Imply FloatMF. + (i386_optab): Split reg and mem forms of moving from segment registers + so that the memory forms can ignore the 16-/32-bit operand size + distinction. Adjust a few others for Intel mode. Remove *FP uses from + all non-floating-point instructions. Unite 32- and 64-bit forms of + movsx, movzx, and movd. Adjust floating point operations for the above + changes to the *FP macros. Add DefaultSize to floating point control + insns operating on larger memory ranges. Remove left over comments + hinting at certain insns being Intel-syntax ones where the ones + actually meant are already gone. + +2004-10-07 Tomer Levi <Tomer.Levi@nsc.com> + + * crx.h: Add COPS_REG_INS - Coprocessor Special register + instruction type. + +2004-09-30 Paul Brook <paul@codesourcery.com> + + * arm.h (ARM_EXT_V6K, ARM_EXT_V6Z): Define. + (ARM_ARCH_V6K, ARM_ARCH_V6Z, ARM_ARCH_V6ZK): Define. + +2004-09-11 Theodore A. Roth <troth@openavr.org> + + * avr.h: Add support for + atmega48, atmega88, atmega168, attiny13, attiny2313, at90can128. + +2004-09-09 Segher Boessenkool <segher@kernel.crashing.org> + + * ppc.h (PPC_OPERAND_OPTIONAL): Fix comment. + +2004-08-24 Dmitry Diky <diwil@spec.ru> + + * msp430.h (msp430_opc): Add new instructions. + (msp430_rcodes): Declare new instructions. + (msp430_hcodes): Likewise.. + +2004-08-13 Nick Clifton <nickc@redhat.com> + + PR/301 + * h8300.h (O_JSR): Do not allow VECIND addressing for non-SX + processors. + +2004-08-30 Michal Ludvig <mludvig@suse.cz> + + * i386.h (i386_optab): Added montmul/xsha1/xsha256 insns. + +2004-07-22 H.J. Lu <hongjiu.lu@intel.com> + + * i386.h (i386_optab): Allow cs/ds in 64bit for branch hints. + +2004-07-21 Jan Beulich <jbeulich@novell.com> + + * i386.h: Adjust instruction descriptions to better match the + specification. + +2004-07-16 Richard Earnshaw <rearnsha@arm.com> + + * arm.h: Remove all old content. Replace with architecture defines + from gas/config/tc-arm.c. + +2004-07-09 Andreas Schwab <schwab@suse.de> + + * m68k.h: Fix comment. + +2004-07-07 Tomer Levi <Tomer.Levi@nsc.com> + + * crx.h: New file. + +2004-06-24 Alan Modra <amodra@bigpond.net.au> + + * i386.h (i386_optab): Remove fildd, fistpd and fisttpd. + +2004-05-24 Peter Barada <peter@the-baradas.com> + + * m68k.h: Add 'size' to m68k_opcode. + +2004-05-05 Peter Barada <peter@the-baradas.com> + + * m68k.h: Switch from ColdFire chip name to core variant. + +2004-04-22 Peter Barada <peter@the-baradas.com> + + * m68k.h: Add mcfmac/mcfemac definitions. Update operand + descriptions for new EMAC cases. + Remove ColdFire macmw/macml/msacmw/msacmw hacks and properly + handle Motorola MAC syntax. + Allow disassembly of ColdFire V4e object files. 2004-03-16 Alan Modra <amodra@bigpond.net.au> * ppc.h (PPC_OPERAND_GPR_0): Define. Bump other operand defines. +2004-03-12 Jakub Jelinek <jakub@redhat.com> + + * i386.h (i386_optab): Remove CpuNo64 from sysenter and sysexit. + 2004-03-12 Michal Ludvig <mludvig@suse.cz> * i386.h (i386_optab): Added xstore as an alias for xstorerng. diff --git a/gnu/dist/binutils/include/opcode/arm.h b/gnu/dist/binutils/include/opcode/arm.h index 99bb9a64f01..dd90e2ac669 100644 --- a/gnu/dist/binutils/include/opcode/arm.h +++ b/gnu/dist/binutils/include/opcode/arm.h @@ -1,294 +1,96 @@ -/* ARM opcode list. - Copyright 1989, 1991 Free Software Foundation, Inc. - -This file is part of GDB and GAS. - -GDB and GAS are free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 1, or (at your option) -any later version. - -GDB and GAS are distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. - -You should have received a copy of the GNU General Public License -along with GDB or GAS; see the file COPYING. If not, write to -the Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ - -/* types of instruction (encoded in bits 26 and 27 of the instruction) */ - -#define TYPE_ARITHMETIC 0 -#define TYPE_LDR_STR 1 -#define TYPE_BLOCK_BRANCH 2 -#define TYPE_SWI 3 - -/* bit 25 decides whether an instruction is a block move or a branch */ -#define SUBTYPE_BLOCK 0 -#define SUBTYPE_BRANCH 1 - -/* codes to distinguish the arithmetic instructions */ - -#define OPCODE_AND 0 -#define OPCODE_EOR 1 -#define OPCODE_SUB 2 -#define OPCODE_RSB 3 -#define OPCODE_ADD 4 -#define OPCODE_ADC 5 -#define OPCODE_SBC 6 -#define OPCODE_RSC 7 -#define OPCODE_TST 8 -#define OPCODE_TEQ 9 -#define OPCODE_CMP 10 -#define OPCODE_CMN 11 -#define OPCODE_ORR 12 -#define OPCODE_MOV 13 -#define OPCODE_BIC 14 -#define OPCODE_MVN 15 - -/* condition codes */ - -#define COND_EQ 0 -#define COND_NE 1 -#define COND_CS 2 -#define COND_CC 3 -#define COND_MI 4 -#define COND_PL 5 -#define COND_VS 6 -#define COND_VC 7 -#define COND_HI 8 -#define COND_LS 9 -#define COND_GE 10 -#define COND_LT 11 -#define COND_GT 12 -#define COND_LE 13 -#define COND_AL 14 -#define COND_NV 15 - -/* Describes the format of an ARM machine instruction */ - -struct generic_fmt { - unsigned rest :25; /* the rest of the instruction */ - unsigned subtype :1; /* used to decide between block and branch */ - unsigned type :2; /* one of TYPE_* */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct arith_fmt { - unsigned operand2 :12; /* #nn or rn or rn shift #m or rn shift rm */ - unsigned dest :4; /* place where the answer goes */ - unsigned operand1 :4; /* first operand to instruction */ - unsigned set :1; /* == 1 means set processor flags */ - unsigned opcode :4; /* one of OPCODE_* defined above */ - unsigned immed :1; /* operand2 is an immediate value */ - unsigned type :2; /* == TYPE_ARITHMETIC */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct ldr_str_fmt { - unsigned offset :12; /* #nn or rn or rn shift #m */ - unsigned reg :4; /* destination for LDR, source for STR */ - unsigned base :4; /* base register */ - unsigned is_load :1; /* == 1 for LDR */ - unsigned writeback :1; /* == 1 means write back (base+offset) into base */ - unsigned byte :1; /* == 1 means byte access else word */ - unsigned up :1; /* == 1 means add offset else subtract it */ - unsigned pre_index :1; /* == 1 means [a,b] form else [a],b form */ - unsigned immed :1; /* == 0 means immediate offset */ - unsigned type :2; /* == TYPE_LDR_STR */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct block_fmt { - unsigned mask :16; /* register mask */ - unsigned base :4; /* register used as base of move */ - unsigned is_load :1; /* == 1 for LDM */ - unsigned writeback :1; /* == 1 means update base after move */ - unsigned set :1; /* == 1 means set flags in pc if included in mask */ - unsigned increment :1; /* == 1 means increment base register */ - unsigned before :1; /* == 1 means inc/dec before each move */ - unsigned is_block :1; /* == SUBTYPE_BLOCK */ - unsigned type :2; /* == TYPE_BLOCK_BRANCH */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -struct branch_fmt { - unsigned dest :24; /* destination of the branch */ - unsigned link :1; /* branch with link (function call) */ - unsigned is_branch :1; /* == SUBTYPE_BRANCH */ - unsigned type :2; /* == TYPE_BLOCK_BRANCH */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -#define ROUND_N 0 -#define ROUND_P 1 -#define ROUND_M 2 -#define ROUND_Z 3 - -#define FLOAT2_MVF 0 -#define FLOAT2_MNF 1 -#define FLOAT2_ABS 2 -#define FLOAT2_RND 3 -#define FLOAT2_SQT 4 -#define FLOAT2_LOG 5 -#define FLOAT2_LGN 6 -#define FLOAT2_EXP 7 -#define FLOAT2_SIN 8 -#define FLOAT2_COS 9 -#define FLOAT2_TAN 10 -#define FLOAT2_ASN 11 -#define FLOAT2_ACS 12 -#define FLOAT2_ATN 13 - -#define FLOAT3_ADF 0 -#define FLOAT3_MUF 1 -#define FLOAT3_SUF 2 -#define FLOAT3_RSF 3 -#define FLOAT3_DVF 4 -#define FLOAT3_RDF 5 -#define FLOAT3_POW 6 -#define FLOAT3_RPW 7 -#define FLOAT3_RMF 8 -#define FLOAT3_FML 9 -#define FLOAT3_FDV 10 -#define FLOAT3_FRD 11 -#define FLOAT3_POL 12 - -struct float2_fmt { - unsigned operand2 :3; /* second operand */ - unsigned immed :1; /* == 1 if second operand is a constant */ - unsigned pad1 :1; /* == 0 */ - unsigned rounding :2; /* ROUND_* */ - unsigned is_double :1; /* == 1 if precision is double (only if not extended) */ - unsigned pad2 :4; /* == 1 */ - unsigned dest :3; /* destination */ - unsigned is_2_op :1; /* == 1 if 2 operand ins */ - unsigned operand1 :3; /* first operand (only of is_2_op == 0) */ - unsigned is_extended :1; /* == 1 if precision is extended */ - unsigned opcode :4; /* FLOAT2_* or FLOAT3_* depending on is_2_op */ - unsigned must_be_2 :2; /* == 2 */ - unsigned type :2; /* == TYPE_SWI */ - unsigned cond :4; /* COND_* */ -}; - -struct swi_fmt { - unsigned argument :24; /* argument to SWI (syscall number) */ - unsigned must_be_3 :2; /* == 3 */ - unsigned type :2; /* == TYPE_SWI */ - unsigned cond :4; /* one of COND_* defined above */ -}; - -union insn_fmt { - struct generic_fmt generic; - struct arith_fmt arith; - struct ldr_str_fmt ldr_str; - struct block_fmt block; - struct branch_fmt branch; - struct swi_fmt swi; - unsigned long ins; -}; - -struct opcode { - unsigned long value, mask; /* recognise instruction if (op&mask)==value */ - char *assembler; /* how to disassemble this instruction */ -}; - -/* format of the assembler string : - - %% % - %<bitfield>d print the bitfield in decimal - %<bitfield>x print the bitfield in hex - %<bitfield>r print as an ARM register - %<bitfield>f print a floating point constant if >7 else an fp register - %c print condition code (always bits 28-31) - %P print floating point precision in arithmetic insn - %Q print floating point precision in ldf/stf insn - %R print floating point rounding mode - %<bitnum>'c print specified char iff bit is one - %<bitnum>`c print specified char iff bit is zero - %<bitnum>?ab print a if bit is one else print b - %p print 'p' iff bits 12-15 are 15 - %o print operand2 (immediate or register + shift) - %a print address for ldr/str instruction - %b print branch destination - %A print address for ldc/stc/ldf/stf instruction - %m print register mask for ldm/stm instruction -*/ - -static struct opcode opcodes[] = { - /* ARM instructions */ - 0x00000090, 0x0fe000f0, "mul%20's %12-15r, %16-19r, %0-3r", - 0x00200090, 0x0fe000f0, "mla%20's %12-15r, %16-19r, %0-3r, %8-11r", - 0x00000000, 0x0de00000, "and%c%20's %12-15r, %16-19r, %o", - 0x00200000, 0x0de00000, "eor%c%20's %12-15r, %16-19r, %o", - 0x00400000, 0x0de00000, "sub%c%20's %12-15r, %16-19r, %o", - 0x00600000, 0x0de00000, "rsb%c%20's %12-15r, %16-19r, %o", - 0x00800000, 0x0de00000, "add%c%20's %12-15r, %16-19r, %o", - 0x00a00000, 0x0de00000, "adc%c%20's %12-15r, %16-19r, %o", - 0x00c00000, 0x0de00000, "sbc%c%20's %12-15r, %16-19r, %o", - 0x00e00000, 0x0de00000, "rsc%c%20's %12-15r, %16-19r, %o", - 0x01000000, 0x0de00000, "tst%c%p %16-19r, %o", - 0x01200000, 0x0de00000, "teq%c%p %16-19r, %o", - 0x01400000, 0x0de00000, "cmp%c%p %16-19r, %o", - 0x01600000, 0x0de00000, "cmn%c%p %16-19r, %o", - 0x01800000, 0x0de00000, "orr%c%20's %12-15r, %16-19r, %o", - 0x01a00000, 0x0de00000, "mov%c%20's %12-15r, %o", - 0x01c00000, 0x0de00000, "bic%c%20's %12-15r, %16-19r, %o", - 0x01e00000, 0x0de00000, "mvn%c%20's %12-15r, %o", - 0x04000000, 0x0c100000, "str%c%22'b %12-15r, %a", - 0x04100000, 0x0c100000, "ldr%c%22'b %12-15r, %a", - 0x08000000, 0x0e100000, "stm%c%23?id%24?ba %16-19r%22`!, %m", - 0x08100000, 0x0e100000, "ldm%c%23?id%24?ba %16-19r%22`!, %m%22'^", - 0x0a000000, 0x0e000000, "b%c%24'l %b", - 0x0f000000, 0x0f000000, "swi%c %0-23x", - /* Floating point coprocessor instructions */ - 0x0e000100, 0x0ff08f10, "adf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e100100, 0x0ff08f10, "muf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e200100, 0x0ff08f10, "suf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e300100, 0x0ff08f10, "rsf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e400100, 0x0ff08f10, "dvf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e500100, 0x0ff08f10, "rdf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e600100, 0x0ff08f10, "pow%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e700100, 0x0ff08f10, "rpw%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e800100, 0x0ff08f10, "rmf%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e900100, 0x0ff08f10, "fml%c%P%R %12-14f, %16-18f, %0-3f", - 0x0ea00100, 0x0ff08f10, "fdv%c%P%R %12-14f, %16-18f, %0-3f", - 0x0eb00100, 0x0ff08f10, "frd%c%P%R %12-14f, %16-18f, %0-3f", - 0x0ec00100, 0x0ff08f10, "pol%c%P%R %12-14f, %16-18f, %0-3f", - 0x0e008100, 0x0ff08f10, "mvf%c%P%R %12-14f, %0-3f", - 0x0e108100, 0x0ff08f10, "mnf%c%P%R %12-14f, %0-3f", - 0x0e208100, 0x0ff08f10, "abs%c%P%R %12-14f, %0-3f", - 0x0e308100, 0x0ff08f10, "rnd%c%P%R %12-14f, %0-3f", - 0x0e408100, 0x0ff08f10, "sqt%c%P%R %12-14f, %0-3f", - 0x0e508100, 0x0ff08f10, "log%c%P%R %12-14f, %0-3f", - 0x0e608100, 0x0ff08f10, "lgn%c%P%R %12-14f, %0-3f", - 0x0e708100, 0x0ff08f10, "exp%c%P%R %12-14f, %0-3f", - 0x0e808100, 0x0ff08f10, "sin%c%P%R %12-14f, %0-3f", - 0x0e908100, 0x0ff08f10, "cos%c%P%R %12-14f, %0-3f", - 0x0ea08100, 0x0ff08f10, "tan%c%P%R %12-14f, %0-3f", - 0x0eb08100, 0x0ff08f10, "asn%c%P%R %12-14f, %0-3f", - 0x0ec08100, 0x0ff08f10, "acs%c%P%R %12-14f, %0-3f", - 0x0ed08100, 0x0ff08f10, "atn%c%P%R %12-14f, %0-3f", - 0x0e000110, 0x0ff00f1f, "flt%c%P%R %16-18f, %12-15r", - 0x0e100110, 0x0fff0f98, "fix%c%R %12-15r, %0-2f", - 0x0e200110, 0x0fff0fff, "wfs%c %12-15r", - 0x0e300110, 0x0fff0fff, "rfs%c %12-15r", - 0x0e400110, 0x0fff0fff, "wfc%c %12-15r", - 0x0e500110, 0x0fff0fff, "rfc%c %12-15r", - 0x0e90f110, 0x0ff8fff0, "cmf%c %16-18f, %0-3f", - 0x0eb0f110, 0x0ff8fff0, "cnf%c %16-18f, %0-3f", - 0x0ed0f110, 0x0ff8fff0, "cmfe%c %16-18f, %0-3f", - 0x0ef0f110, 0x0ff8fff0, "cnfe%c %16-18f, %0-3f", - 0x0c000100, 0x0e100f00, "stf%c%Q %12-14f, %A", - 0x0c100100, 0x0e100f00, "ldf%c%Q %12-14f, %A", - /* Generic coprocessor instructions */ - 0x0e000000, 0x0f000010, "cdp%c %8-11d, %20-23d, cr%12-15d, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0e000010, 0x0f100010, "mrc%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0e100010, 0x0f100010, "mcr%c %8-11d, %21-23d, %12-15r, cr%16-19d, cr%0-3d, {%5-7d}", - 0x0c000000, 0x0e100000, "stc%c%22`l %8-11d, cr%12-15d, %A", - 0x0c100000, 0x0e100000, "ldc%c%22`l %8-11d, cr%12-15d, %A", - /* the rest */ - 0x00000000, 0x00000000, "undefined instruction %0-31x", -}; -#define N_OPCODES (sizeof opcodes / sizeof opcodes[0]) +/* ARM assembler/disassembler support. + Copyright 2004 Free Software Foundation, Inc. + + This file is part of GDB and GAS. + + GDB and GAS are free software; you can redistribute it and/or + modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 1, or (at + your option) any later version. + + GDB and GAS are distributed in the hope that it will be useful, but + WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + General Public License for more details. + + You should have received a copy of the GNU General Public License + along with GDB or GAS; see the file COPYING. If not, write to the + Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA + 02111-1307, USA. */ + +/* The following bitmasks control CPU extensions: */ +#define ARM_EXT_V1 0x00000001 /* All processors (core set). */ +#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */ +#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */ +#define ARM_EXT_V3 0x00000008 /* MSR MRS. */ +#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */ +#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */ +#define ARM_EXT_V4T 0x00000040 /* Thumb v1. */ +#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */ +#define ARM_EXT_V5T 0x00000100 /* Thumb v2. */ +#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */ +#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */ +#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */ +#define ARM_EXT_V6 0x00001000 /* ARM V6. */ +#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */ +#define ARM_EXT_V6Z 0x00004000 /* ARM V6Z. */ + +/* Co-processor space extensions. */ +#define ARM_CEXT_XSCALE 0x00800000 /* Allow MIA etc. */ +#define ARM_CEXT_MAVERICK 0x00400000 /* Use Cirrus/DSP coprocessor. */ +#define ARM_CEXT_IWMMXT 0x00200000 /* Intel Wireless MMX technology coprocessor. */ + +/* Architectures are the sum of the base and extensions. The ARM ARM (rev E) + defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T, + ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add + three more to cover cores prior to ARM6. Finally, there are cores which + implement further extensions in the co-processor space. */ +#define ARM_ARCH_V1 ARM_EXT_V1 +#define ARM_ARCH_V2 (ARM_ARCH_V1 | ARM_EXT_V2) +#define ARM_ARCH_V2S (ARM_ARCH_V2 | ARM_EXT_V2S) +#define ARM_ARCH_V3 (ARM_ARCH_V2S | ARM_EXT_V3) +#define ARM_ARCH_V3M (ARM_ARCH_V3 | ARM_EXT_V3M) +#define ARM_ARCH_V4xM (ARM_ARCH_V3 | ARM_EXT_V4) +#define ARM_ARCH_V4 (ARM_ARCH_V3M | ARM_EXT_V4) +#define ARM_ARCH_V4TxM (ARM_ARCH_V4xM | ARM_EXT_V4T) +#define ARM_ARCH_V4T (ARM_ARCH_V4 | ARM_EXT_V4T) +#define ARM_ARCH_V5xM (ARM_ARCH_V4xM | ARM_EXT_V5) +#define ARM_ARCH_V5 (ARM_ARCH_V4 | ARM_EXT_V5) +#define ARM_ARCH_V5TxM (ARM_ARCH_V5xM | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_ARCH_V5T (ARM_ARCH_V5 | ARM_EXT_V4T | ARM_EXT_V5T) +#define ARM_ARCH_V5TExP (ARM_ARCH_V5T | ARM_EXT_V5ExP) +#define ARM_ARCH_V5TE (ARM_ARCH_V5TExP | ARM_EXT_V5E) +#define ARM_ARCH_V5TEJ (ARM_ARCH_V5TE | ARM_EXT_V5J) +#define ARM_ARCH_V6 (ARM_ARCH_V5TEJ | ARM_EXT_V6) +#define ARM_ARCH_V6K (ARM_ARCH_V6 | ARM_EXT_V6K) +#define ARM_ARCH_V6Z (ARM_ARCH_V6 | ARM_EXT_V6Z) +#define ARM_ARCH_V6ZK (ARM_ARCH_V6 | ARM_EXT_V6K | ARM_EXT_V6Z) + +/* Processors with specific extensions in the co-processor space. */ +#define ARM_ARCH_XSCALE (ARM_ARCH_V5TE | ARM_CEXT_XSCALE) +#define ARM_ARCH_IWMMXT (ARM_ARCH_XSCALE | ARM_CEXT_IWMMXT) + +#define FPU_FPA_EXT_V1 0x80000000 /* Base FPA instruction set. */ +#define FPU_FPA_EXT_V2 0x40000000 /* LFM/SFM. */ +#define FPU_VFP_EXT_NONE 0x20000000 /* Use VFP word-ordering. */ +#define FPU_VFP_EXT_V1xD 0x10000000 /* Base VFP instruction set. */ +#define FPU_VFP_EXT_V1 0x08000000 /* Double-precision insns. */ +#define FPU_VFP_EXT_V2 0x04000000 /* ARM10E VFPr1. */ +#define FPU_MAVERICK 0x02000000 /* Cirrus Maverick. */ +#define FPU_NONE 0 + +#define FPU_ARCH_FPE FPU_FPA_EXT_V1 +#define FPU_ARCH_FPA (FPU_ARCH_FPE | FPU_FPA_EXT_V2) + +#define FPU_ARCH_VFP FPU_VFP_EXT_NONE +#define FPU_ARCH_VFP_V1xD (FPU_VFP_EXT_V1xD | FPU_VFP_EXT_NONE) +#define FPU_ARCH_VFP_V1 (FPU_ARCH_VFP_V1xD | FPU_VFP_EXT_V1) +#define FPU_ARCH_VFP_V2 (FPU_ARCH_VFP_V1 | FPU_VFP_EXT_V2) + +#define FPU_ARCH_MAVERICK FPU_MAVERICK + +/* Some useful combinations: */ +#define ARM_ANY 0x0000ffff /* Any basic core. */ +#define ARM_ALL 0x00ffffff /* Any core + co-processor */ +#define CPROC_ANY 0x00ff0000 /* Any co-processor */ +#define FPU_ANY 0xff000000 /* Note this is ~ARM_ALL. */ diff --git a/gnu/dist/binutils/include/opcode/avr.h b/gnu/dist/binutils/include/opcode/avr.h index bcc093d302b..6e93b73d46e 100644 --- a/gnu/dist/binutils/include/opcode/avr.h +++ b/gnu/dist/binutils/include/opcode/avr.h @@ -1,6 +1,6 @@ /* Opcode table for the Atmel AVR micro controllers. - Copyright 2000 Free Software Foundation, Inc. + Copyright 2000, 2001, 2004 Free Software Foundation, Inc. Contributed by Denis Chertykov <denisc@overta.ru> This program is free software; you can redistribute it and/or modify @@ -23,20 +23,25 @@ #define AVR_ISA_SRAM 0x0008 /* device has SRAM (LD, ST, PUSH, POP, ...) */ #define AVR_ISA_MEGA 0x0020 /* device has >8K program memory (JMP and CALL supported, no 8K wrap on RJMP and RCALL) */ -#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, MOVW, ...) */ +#define AVR_ISA_MUL 0x0040 /* device has new core (MUL, FMUL, ...) */ #define AVR_ISA_ELPM 0x0080 /* device has >64K program memory (ELPM) */ #define AVR_ISA_ELPMX 0x0100 /* device has ELPM Rd,Z[+] */ #define AVR_ISA_SPM 0x0200 /* device can program itself */ #define AVR_ISA_BRK 0x0400 /* device has BREAK (on-chip debug) */ #define AVR_ISA_EIND 0x0800 /* device has >128K program memory (none yet) */ +#define AVR_ISA_MOVW 0x1000 /* device has MOVW */ #define AVR_ISA_TINY1 (AVR_ISA_1200 | AVR_ISA_LPM) #define AVR_ISA_2xxx (AVR_ISA_TINY1 | AVR_ISA_SRAM) -#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_TINY2 (AVR_ISA_2xxx | AVR_ISA_MOVW | AVR_ISA_LPMX | \ + AVR_ISA_SPM | AVR_ISA_BRK) +#define AVR_ISA_M8 (AVR_ISA_2xxx | AVR_ISA_MUL | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM) #define AVR_ISA_M603 (AVR_ISA_2xxx | AVR_ISA_MEGA) #define AVR_ISA_M103 (AVR_ISA_M603 | AVR_ISA_ELPM) -#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX | AVR_ISA_SPM) -#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_LPMX) +#define AVR_ISA_M161 (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | \ + AVR_ISA_LPMX | AVR_ISA_SPM) +#define AVR_ISA_94K (AVR_ISA_M603 | AVR_ISA_MUL | AVR_ISA_MOVW | AVR_ISA_LPMX) #define AVR_ISA_M323 (AVR_ISA_M161 | AVR_ISA_BRK) #define AVR_ISA_M128 (AVR_ISA_M323 | AVR_ISA_ELPM | AVR_ISA_ELPMX) @@ -236,7 +241,7 @@ AVR_INSN (ror, "r", "1001010rrrrr0111", 1, AVR_ISA_1200, 0x9407) AVR_INSN (swap, "r", "1001010rrrrr0010", 1, AVR_ISA_1200, 0x9402) /* Known to be decoded as `nop' by the old core. */ -AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MUL, 0x0100) +AVR_INSN (movw, "v,v", "00000001ddddrrrr", 1, AVR_ISA_MOVW, 0x0100) AVR_INSN (muls, "d,d", "00000010ddddrrrr", 1, AVR_ISA_MUL, 0x0200) AVR_INSN (mulsu,"a,a", "000000110ddd0rrr", 1, AVR_ISA_MUL, 0x0300) AVR_INSN (fmul, "a,a", "000000110ddd1rrr", 1, AVR_ISA_MUL, 0x0308) diff --git a/gnu/dist/binutils/include/opcode/cgen.h b/gnu/dist/binutils/include/opcode/cgen.h index 16366fd0d75..f9441618a96 100644 --- a/gnu/dist/binutils/include/opcode/cgen.h +++ b/gnu/dist/binutils/include/opcode/cgen.h @@ -1,6 +1,6 @@ /* Header file for targets using CGEN: Cpu tools GENerator. -Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 +Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005 Free Software Foundation, Inc. This file is part of GDB, the GNU debugger, and the GNU Binutils. @@ -369,7 +369,8 @@ enum cgen_parse_operand_type { CGEN_PARSE_OPERAND_INIT, CGEN_PARSE_OPERAND_INTEGER, - CGEN_PARSE_OPERAND_ADDRESS + CGEN_PARSE_OPERAND_ADDRESS, + CGEN_PARSE_OPERAND_SYMBOLIC }; /* Values for indicating what was parsed. */ diff --git a/gnu/dist/binutils/include/opcode/cris.h b/gnu/dist/binutils/include/opcode/cris.h index 1f10034c304..9b33f199c56 100644 --- a/gnu/dist/binutils/include/opcode/cris.h +++ b/gnu/dist/binutils/include/opcode/cris.h @@ -1,5 +1,5 @@ /* cris.h -- Header file for CRIS opcode and register tables. - Copyright (C) 2000, 2001 Free Software Foundation, Inc. + Copyright (C) 2000, 2001, 2004 Free Software Foundation, Inc. Contributed by Axis Communications AB, Lund, Sweden. Originally written for GAS 1.38.1 by Mikael Asker. Updated, BFDized and GNUified by Hans-Peter Nilsson. @@ -38,15 +38,12 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ immediate operands. */ enum cris_insn_version_usage { - /* Any version. */ + /* Any version. */ cris_ver_version_all=0, /* Indeterminate (intended for disassembly only, or obsolete). */ cris_ver_warning, - /* Simulator only (reserved). */ - cris_ver_sim, - /* Only for v0..3 (Etrax 1..4). */ cris_ver_v0_3, @@ -59,10 +56,28 @@ enum cris_insn_version_usage /* Only for v8 or higher (ETRAX 100, ETRAX 100 LX). */ cris_ver_v8p, - /* Only for v10 or higher (ETRAX 100 LX). - Of course some or all these of may change to cris_ver_v10p if/when + /* Only for v0..10. FIXME: Not sure what to do with this. */ + cris_ver_sim_v0_10, + + /* Only for v0..10. */ + cris_ver_v0_10, + + /* Only for v3..10. (ETRAX 4, ETRAX 100 and ETRAX 100 LX). */ + cris_ver_v3_10, + + /* Only for v8..10 (ETRAX 100 and ETRAX 100 LX). */ + cris_ver_v8_10, + + /* Only for v10 (ETRAX 100 LX) and same series. */ + cris_ver_v10, + + /* Only for v10 (ETRAX 100 LX) and same series. */ + cris_ver_v10p, + + /* Only for v32 or higher (codename GUINNESS). + Of course some or all these of may change to cris_ver_v32p if/when there's a new revision. */ - cris_ver_v10p + cris_ver_v32p }; @@ -85,6 +100,25 @@ struct cris_spec_reg }; extern const struct cris_spec_reg cris_spec_regs[]; + +/* Support registers (kind of special too, but not named as such). */ +struct cris_support_reg +{ + const char *const name; + unsigned int number; +}; +extern const struct cris_support_reg cris_support_regs[]; + +struct cris_cond15 +{ + /* The name of the condition. */ + const char *const name; + + /* What CPU version this condition name applies to. */ + enum cris_insn_version_usage applicable_version; +}; +extern const struct cris_cond15 cris_conds15[]; + /* Opcode-dependent constants. */ #define AUTOINCR_BIT (0x04) @@ -163,9 +197,28 @@ extern const char *const cris_cc_strings[]; #define ADD_PC_INCR_OPCODE \ (0xfa00 + (2 << 4) + AUTOINCR_BIT * 0x0100 + REG_PC) +#define JUMP_PC_INCR_OPCODE_V32 (0x0DBF) + +/* BA DWORD (V32). */ +#define BA_DWORD_OPCODE (0x0EBF) + /* Nop. */ #define NOP_OPCODE (0x050F) -#define NOP_Z_BITS (0xFAF0) +#define NOP_Z_BITS (0xFFFF ^ NOP_OPCODE) + +#define NOP_OPCODE_V32 (0x05B0) +#define NOP_Z_BITS_V32 (0xFFFF ^ NOP_OPCODE_V32) + +/* For the compatibility mode, let's use "MOVE R0,P0". Doesn't affect + registers or flags. Unfortunately shuts off interrupts for one cycle + for < v32, but there doesn't seem to be any alternative without that + effect. */ +#define NOP_OPCODE_COMMON (0x630) +#define NOP_OPCODE_ZBITS_COMMON (0xffff & ~NOP_OPCODE_COMMON) + +/* LAPC.D */ +#define LAPC_DWORD_OPCODE (0x0D7F) +#define LAPC_DWORD_Z_BITS (0x0fff & ~LAPC_DWORD_OPCODE) /* Structure of an opcode table entry. */ enum cris_imm_oprnd_size_type @@ -179,7 +232,13 @@ enum cris_imm_oprnd_size_type /* Indicated by size of special register. */ SIZE_SPEC_REG, - /* Indicated by size field. */ + /* Indicated by size field, signed. */ + SIZE_FIELD_SIGNED, + + /* Indicated by size field, unsigned. */ + SIZE_FIELD_UNSIGNED, + + /* Indicated by size field, no sign implied. */ SIZE_FIELD }; diff --git a/gnu/dist/binutils/include/opcode/crx.h b/gnu/dist/binutils/include/opcode/crx.h new file mode 100644 index 00000000000..f0fd41a30cb --- /dev/null +++ b/gnu/dist/binutils/include/opcode/crx.h @@ -0,0 +1,418 @@ +/* crx.h -- Header file for CRX opcode and register tables. + Copyright 2004 Free Software Foundation, Inc. + Contributed by Tomer Levi, NSC, Israel. + Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. + Updates, BFDizing, GNUifying and ELF support by Tomer Levi. + + This file is part of GAS, GDB and the GNU binutils. + + GAS, GDB, and GNU binutils is free software; you can redistribute it + and/or modify it under the terms of the GNU General Public License as + published by the Free Software Foundation; either version 2, or (at your + option) any later version. + + GAS, GDB, and GNU binutils are distributed in the hope that they will be + useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _CRX_H_ +#define _CRX_H_ + +/* CRX core/debug Registers : + The enums are used as indices to CRX registers table (crx_regtab). + Therefore, order MUST be preserved. */ + +typedef enum + { + /* 32-bit general purpose registers. */ + r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, + r10, r11, r12, r13, r14, r15, ra, sp, + /* 32-bit user registers. */ + u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, + u10, u11, u12, u13, u14, u15, ura, usp, + /* hi and lo registers. */ + hi, lo, + /* hi and lo user registers. */ + uhi, ulo, + /* Processor Status Register. */ + psr, + /* Interrupt Base Register. */ + intbase, + /* Interrupt Stack Pointer Register. */ + isp, + /* Configuration Register. */ + cfg, + /* Coprocessor Configuration Register. */ + cpcfg, + /* Coprocessor Enable Register. */ + cen, + /* Not a register. */ + nullregister, + MAX_REG + } +reg; + +/* CRX Coprocessor registers and special registers : + The enums are used as indices to CRX coprocessor registers table + (crx_copregtab). Therefore, order MUST be preserved. */ + +typedef enum + { + /* Coprocessor registers. */ + c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, + c9, c10, c11, c12, c13, c14, c15, + /* Coprocessor special registers. */ + cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, + cs9, cs10, cs11, cs12, cs13, cs14, cs15, + /* Not a Coprocessor register. */ + nullcopregister, + MAX_COPREG + } +copreg; + +/* CRX Register types. */ + +typedef enum + { + CRX_R_REGTYPE, /* r<N> */ + CRX_U_REGTYPE, /* u<N> */ + CRX_C_REGTYPE, /* c<N> */ + CRX_CS_REGTYPE, /* cs<N> */ + CRX_CFG_REGTYPE /* configuration register */ + } +reg_type; + +/* CRX argument types : + The argument types correspond to instructions operands + + Argument types : + r - register + c - constant + i - immediate + idxr - index register + rbase - register base + s - star ('*') + copr - coprocessor register + copsr - coprocessor special register. */ + +typedef enum + { + arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, + arg_idxr, arg_rbase, arg_copr, arg_copsr, + /* Not an argument. */ + nullargs + } +argtype; + +/* CRX operand types : + The operand types correspond to instructions operands. */ + +typedef enum + { + dummy, + /* 4-bit encoded constant. */ + cst4, + /* N-bit immediate. */ + i16, i32, + /* N-bit unsigned immediate. */ + ui3, ui4, ui5, ui16, + /* N-bit signed displacement. */ + disps9, disps17, disps25, disps32, + /* N-bit unsigned displacement. */ + dispu5, + /* N-bit escaped displacement. */ + dispe9, + /* N-bit absolute address. */ + abs16, abs32, + /* Register relative. */ + rbase, rbase_dispu4, + rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, + /* Register index. */ + rindex_disps6, rindex_disps22, + /* 4-bit genaral-purpose register specifier. */ + regr, + /* 8-bit register address space. */ + regr8, + /* coprocessor register. */ + copregr, + /* coprocessor special register. */ + copsregr, + /* Not an operand. */ + nulloperand, + /* Maximum supported operand. */ + MAX_OPRD + } +operand_type; + +/* CRX instruction types. */ + +#define NO_TYPE_INS 0 +#define ARITH_INS 1 +#define LD_STOR_INS 2 +#define BRANCH_INS 3 +#define ARITH_BYTE_INS 4 +#define CMPBR_INS 5 +#define SHIFT_INS 6 +#define BRANCH_NEQ_INS 7 +#define LD_STOR_INS_INC 8 +#define STOR_IMM_INS 9 +#define CSTBIT_INS 10 +#define COP_BRANCH_INS 11 +#define COP_REG_INS 12 +#define COPS_REG_INS 13 +#define DCR_BRANCH_INS 14 + +/* Maximum value supported for instruction types. */ +#define CRX_INS_MAX (1 << 4) +/* Mask to record an instruction type. */ +#define CRX_INS_MASK (CRX_INS_MAX - 1) +/* Return instruction type, given instruction's attributes. */ +#define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) + +/* Indicates whether this instruction has a register list as parameter. */ +#define REG_LIST CRX_INS_MAX +/* The operands in binary and assembly are placed in reverse order. + load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ +#define REVERSE_MATCH (1 << 5) + +/* Kind of displacement map used DISPU[BWD]4. */ +#define DISPUB4 (1 << 6) +#define DISPUW4 (1 << 7) +#define DISPUD4 (1 << 8) +#define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) + +/* Printing formats, where the instruction prefix isn't consecutive. */ +#define FMT_1 (1 << 9) /* 0xF0F00000 */ +#define FMT_2 (1 << 10) /* 0xFFF0FF00 */ +#define FMT_3 (1 << 11) /* 0xFFF00F00 */ +#define FMT_4 (1 << 12) /* 0xFFF0F000 */ +#define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ +#define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) + +/* Indicates whether this instruction can be relaxed. */ +#define RELAXABLE (1 << 14) + +/* Indicates that instruction uses user registers (and not + general-purpose registers) as operands. */ +#define USER_REG (1 << 15) + +/* Indicates that instruction can perfom a cst4 mapping. */ +#define CST4MAP (1 << 16) + +/* Instruction shouldn't allow 'sp' usage. */ +#define NO_SP (1 << 17) + +/* Instruction shouldn't allow to push a register which is used as a rptr. */ +#define NO_RPTR (1 << 18) + +/* Maximum operands per instruction. */ +#define MAX_OPERANDS 5 +/* Maximum register name length. */ +#define MAX_REGNAME_LEN 10 +/* Maximum instruction length. */ +#define MAX_INST_LEN 256 + + +/* Values defined for the flags field of a struct operand_entry. */ + +/* Operand must be an unsigned number. */ +#define OP_UNSIGNED (1 << 0) +/* Operand must be a signed number. */ +#define OP_SIGNED (1 << 1) +/* A special arithmetic 4-bit constant operand. */ +#define OP_CST4 (1 << 2) +/* A special load/stor 4-bit unsigned displacement operand. */ +#define OP_DISPU4 (1 << 3) +/* Operand must be an even number. */ +#define OP_EVEN (1 << 4) +/* Operand is shifted right. */ +#define OP_SHIFT (1 << 5) +/* Operand is shifted right and decremented. */ +#define OP_SHIFT_DEC (1 << 6) +/* Operand has reserved escape sequences. */ +#define OP_ESC (1 << 7) +/* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ +#define OP_UPPER_64KB (1 << 8) + +/* Single operand description. */ + +typedef struct + { + /* Operand type. */ + operand_type op_type; + /* Operand location within the opcode. */ + unsigned int shift; + } +operand_desc; + +/* Instruction data structure used in instruction table. */ + +typedef struct + { + /* Name. */ + const char *mnemonic; + /* Size (in words). */ + unsigned int size; + /* Constant prefix (matched by the disassembler). */ + unsigned long match; + /* Match size (in bits). */ + int match_bits; + /* Attributes. */ + unsigned int flags; + /* Operands (always last, so unreferenced operands are initialized). */ + operand_desc operands[MAX_OPERANDS]; + } +inst; + +/* Data structure for a single instruction's arguments (Operands). */ + +typedef struct + { + /* Register or base register. */ + reg r; + /* Index register. */ + reg i_r; + /* Coprocessor register. */ + copreg cr; + /* Constant/immediate/absolute value. */ + long constant; + /* Scaled index mode. */ + unsigned int scale; + /* Argument type. */ + argtype type; + /* Size of the argument (in bits) required to represent. */ + int size; + /* The type of the expression. */ + unsigned char X_op; + } +argument; + +/* Internal structure to hold the various entities + corresponding to the current assembling instruction. */ + +typedef struct + { + /* Number of arguments. */ + int nargs; + /* The argument data structure for storing args (operands). */ + argument arg[MAX_OPERANDS]; +/* The following fields are required only by CRX-assembler. */ +#ifdef TC_CRX + /* Expression used for setting the fixups (if any). */ + expressionS exp; + bfd_reloc_code_real_type rtype; +#endif /* TC_CRX */ + /* Instruction size (in bytes). */ + int size; + } +ins; + +/* Structure to hold information about predefined operands. */ + +typedef struct + { + /* Size (in bits). */ + unsigned int bit_size; + /* Argument type. */ + argtype arg_type; + /* One bit syntax flags. */ + int flags; + } +operand_entry; + +/* Structure to hold trap handler information. */ + +typedef struct + { + /* Trap name. */ + char *name; + /* Index in dispatch table. */ + unsigned int entry; + } +trap_entry; + +/* Structure to hold information about predefined registers. */ + +typedef struct + { + /* Name (string representation). */ + char *name; + /* Value (enum representation). */ + union + { + /* Register. */ + reg reg_val; + /* Coprocessor register. */ + copreg copreg_val; + } value; + /* Register image. */ + int image; + /* Register type. */ + reg_type type; + } +reg_entry; + +/* Structure to hold a cst4 operand mapping. */ + +/* CRX opcode table. */ +extern const inst crx_instruction[]; +extern const int crx_num_opcodes; +#define NUMOPCODES crx_num_opcodes + +/* CRX operands table. */ +extern const operand_entry crx_optab[]; + +/* CRX registers table. */ +extern const reg_entry crx_regtab[]; +extern const int crx_num_regs; +#define NUMREGS crx_num_regs + +/* CRX coprocessor registers table. */ +extern const reg_entry crx_copregtab[]; +extern const int crx_num_copregs; +#define NUMCOPREGS crx_num_copregs + +/* CRX trap/interrupt table. */ +extern const trap_entry crx_traps[]; +extern const int crx_num_traps; +#define NUMTRAPS crx_num_traps + +/* cst4 operand mapping. */ +extern const long cst4_map[]; +extern const int cst4_maps; + +/* Table of instructions with no operands. */ +extern const char* no_op_insn[]; + +/* Current instruction we're assembling. */ +extern const inst *instruction; + +/* A macro for representing the instruction "constant" opcode, that is, + the FIXED part of the instruction. The "constant" opcode is represented + as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) + over that range. */ +#define BIN(OPC,SHIFT) (OPC << SHIFT) + +/* Is the current instruction type is TYPE ? */ +#define IS_INSN_TYPE(TYPE) \ + (CRX_INS_TYPE(instruction->flags) == TYPE) + +/* Is the current instruction mnemonic is MNEMONIC ? */ +#define IS_INSN_MNEMONIC(MNEMONIC) \ + (strcmp(instruction->mnemonic,MNEMONIC) == 0) + +/* Does the current instruction has register list ? */ +#define INST_HAS_REG_LIST \ + (instruction->flags & REG_LIST) + +/* Long long type handling. */ +/* Replace all appearances of 'long long int' with LONGLONG. */ +typedef long long int LONGLONG; +typedef unsigned long long ULONGLONG; + +#endif /* _CRX_H_ */ diff --git a/gnu/dist/binutils/include/opcode/h8300.h b/gnu/dist/binutils/include/opcode/h8300.h index 29374df5b4f..2bc7b44bc30 100644 --- a/gnu/dist/binutils/include/opcode/h8300.h +++ b/gnu/dist/binutils/include/opcode/h8300.h @@ -1,5 +1,6 @@ /* Opcode table for the H8/300 - Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2002, 2003, 2004 + Copyright 1991, 1992, 1993, 1994, 1996, 1997, 1998, 2000, 2001, 2002, + 2003, 2004 Free Software Foundation, Inc. Written by Steve Chamberlain <sac@cygnus.com>. @@ -1418,7 +1419,7 @@ struct h8_opcode h8_opcodes[] = {O (O_JSR, SN), AV_H8SX, 0, "jsr", {{ABSJMP | L_32, E}}, {{0x5, 0xD, 0x0, 0x8, ABSJMP | L_32, DATA7, E}}}, {O (O_JSR, SN), AV_H8, 8, "jsr", {{MEMIND, E}}, {{0x5, 0xF, SRC | MEMIND, DATA, E}}}, - {O (O_JSR, SN), AV_H8, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, + {O (O_JSR, SN), AV_H8SX, 8, "jsr", {{VECIND, E}}, {{0x5, 0xD, SRC | VECIND, DATA, E}}}, {O (O_LDC, SB), AV_H8, 2, "ldc", {{IMM8, CCR | DST, E}}, {{ 0x0, 0x7, IMM8LIST, E}}}, {O (O_LDC, SB), AV_H8S, 2, "ldc", {{IMM8, EXR | DST, E}}, {{0x0, 0x1, 0x4, EXR | DST, 0x0, 0x7, IMM8LIST, E}}}, diff --git a/gnu/dist/binutils/include/opcode/hppa.h b/gnu/dist/binutils/include/opcode/hppa.h index 8234664a626..312cb7f7c44 100644 --- a/gnu/dist/binutils/include/opcode/hppa.h +++ b/gnu/dist/binutils/include/opcode/hppa.h @@ -1,6 +1,6 @@ /* Table of opcodes for the PA-RISC. Copyright 1990, 1991, 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, - 2001, 2002 + 2001, 2002, 2003 Free Software Foundation, Inc. Contributed by the Center for Software Science at the diff --git a/gnu/dist/binutils/include/opcode/i386.h b/gnu/dist/binutils/include/opcode/i386.h index 5e3673e2b04..07163f07754 100644 --- a/gnu/dist/binutils/include/opcode/i386.h +++ b/gnu/dist/binutils/include/opcode/i386.h @@ -1,23 +1,23 @@ /* opcode/i386.h -- Intel 80386 opcode table Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, - 2000, 2001, 2002, 2003, 2004 + 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc. -This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. + This file is part of GAS, the GNU Assembler, and GDB, the GNU Debugger. -This program is free software; you can redistribute it and/or modify -it under the terms of the GNU General Public License as published by -the Free Software Foundation; either version 2 of the License, or -(at your option) any later version. + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. -This program is distributed in the hope that it will be useful, -but WITHOUT ANY WARRANTY; without even the implied warranty of -MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -GNU General Public License for more details. + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. -You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ /* The SystemV/386 SVR3.2 assembler, and probably all AT&T derived ix86 Unix assemblers, generate floating point instructions with @@ -48,7 +48,8 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #define OLDGCC_COMPAT SYSV386_COMPAT #endif -static const template i386_optab[] = { +static const template i386_optab[] = +{ #define X None #define NoSuf (No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_xSuf|No_qSuf) @@ -64,13 +65,13 @@ static const template i386_optab[] = { #define lq_Suf (No_bSuf|No_wSuf|No_sSuf|No_xSuf) #define wq_Suf (No_bSuf|No_lSuf|No_sSuf|No_xSuf) #define sl_Suf (No_bSuf|No_wSuf|No_xSuf|No_qSuf) -#define sldx_Suf (No_bSuf|No_wSuf|No_qSuf) #define bwl_Suf (No_sSuf|No_xSuf|No_qSuf) #define bwlq_Suf (No_sSuf|No_xSuf) -#define FP (NoSuf|IgnoreSize) -#define l_FP (l_Suf|IgnoreSize) -#define x_FP (x_Suf|IgnoreSize) -#define sl_FP (sl_Suf|IgnoreSize) +#define FP (NoSuf) +#define l_FP (l_Suf) +#define q_FP (q_Suf|NoRex64) +#define x_FP (x_Suf|FloatMF) +#define sl_FP (sl_Suf|FloatMF) #if SYSV386_COMPAT /* Someone forgot that the FloatR bit reverses the operation when not equal to the FloatD bit. ie. Changing only FloatD results in the @@ -84,7 +85,7 @@ static const template i386_optab[] = { #define MOV_AX_DISP32 0xa0 /* In the 64bit mode the short form mov immediate is redefined to have 64bit displacement value. */ -{ "mov", 2, 0xa0, X, CpuNo64,bwlq_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, +{ "mov", 2, 0xa0, X, CpuNo64,bwl_Suf|D|W, { Disp16|Disp32, Acc, 0 } }, { "mov", 2, 0x88, X, 0, bwlq_Suf|D|W|Modrm, { Reg, Reg|AnyMem, 0} }, /* In the 64bit mode the short form mov immediate is redefined to have 64bit displacement value. */ @@ -96,8 +97,10 @@ static const template i386_optab[] = { size prefix. When moving to a 32 bit register, the upper 16 bits are set to an implementation defined value (on the Pentium Pro, the implementation defined value is zero). */ -{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|WordMem, 0 } }, -{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|WordMem, 0 } }, +{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm, { SReg2, WordReg|InvMem, 0 } }, +{ "mov", 2, 0x8c, X, 0, wl_Suf|Modrm|IgnoreSize, { SReg2, WordMem, 0 } }, +{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm, { SReg3, WordReg|InvMem, 0 } }, +{ "mov", 2, 0x8c, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { SReg3, WordMem, 0 } }, { "mov", 2, 0x8e, X, 0, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg2, 0 } }, { "mov", 2, 0x8e, X, Cpu386, wl_Suf|Modrm|IgnoreSize, { WordReg|WordMem, SReg3, 0 } }, /* Move to/from control debug registers. In the 16 or 32bit modes they are 32bit. In the 64bit @@ -106,7 +109,7 @@ static const template i386_optab[] = { { "mov", 2, 0x0f20, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Control, Reg64|InvMem, 0} }, { "mov", 2, 0x0f21, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize,{ Debug, Reg32|InvMem, 0} }, { "mov", 2, 0x0f21, X, Cpu64, q_Suf|D|Modrm|IgnoreSize|NoRex64,{ Debug, Reg64|InvMem, 0} }, -{ "mov", 2, 0x0f24, X, Cpu386, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, +{ "mov", 2, 0x0f24, X, Cpu386|CpuNo64, l_Suf|D|Modrm|IgnoreSize, { Test, Reg32|InvMem, 0} }, { "movabs",2, 0xa0, X, Cpu64, bwlq_Suf|D|W, { Disp64, Acc, 0 } }, { "movabs",2, 0xb0, X, Cpu64, q_Suf|W|ShortForm, { Imm64, Reg64, 0 } }, @@ -119,42 +122,41 @@ static const template i386_optab[] = { {"movsbq", 2, 0x0fbe, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, {"movswq", 2, 0x0fbf, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem,Reg64, 0} }, {"movslq", 2, 0x63, X, Cpu64, NoSuf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, -/* Intel Syntax next 5 insns */ +/* Intel Syntax next 3 insns */ {"movsx", 2, 0x0fbe, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -{"movsx", 2, 0x0fbe, X, Cpu64, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movsx", 2, 0x0fbf, X, Cpu64, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, +{"movsx", 2, 0x0fbf, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, {"movsx", 2, 0x63, X, Cpu64, l_Suf|Modrm|Rex64, { Reg32|WordMem, Reg64, 0} }, -/* Move with zero extend. */ +/* Move with zero extend. We can't remove "movzb" since existing + assembly codes may use it. */ {"movzb", 2, 0x0fb6, X, Cpu386, wl_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, +/* "movzbl" & "movzbw" should not be unified into "movzb" for + consistency with the sign extending moves above. */ +{"movzbl", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg32, 0} }, +{"movzbw", 2, 0x0fb6, X, Cpu386, NoSuf|Modrm, { Reg8|ByteMem, Reg16, 0} }, {"movzwl", 2, 0x0fb7, X, Cpu386, NoSuf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* These instructions are not particulary usefull, since the zero extend +/* These instructions are not particulary useful, since the zero extend 32->64 is implicit, but we can encode them. */ {"movzbq", 2, 0x0fb6, X, Cpu64, NoSuf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, {"movzwq", 2, 0x0fb7, X, Cpu64, NoSuf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, -/* Intel Syntax next 4 insns */ +/* Intel Syntax next 2 insns (the 64-bit variants are not particulary useful, + since the zero extend 32->64 is implicit, but we can encode them). */ {"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm, { Reg8|ByteMem, WordReg, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32, 0} }, -/* These instructions are not particulary usefull, since the zero extend - 32->64 is implicit, but we can encode them. */ -{"movzx", 2, 0x0fb6, X, Cpu386, b_Suf|Modrm|Rex64, { Reg8|ByteMem, Reg64, 0} }, -{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm|Rex64, { Reg16|ShortMem, Reg64, 0} }, +{"movzx", 2, 0x0fb7, X, Cpu386, w_Suf|Modrm, { Reg16|ShortMem, Reg32|Reg64, 0} }, /* Push instructions. */ {"push", 1, 0x50, X, CpuNo64, wl_Suf|ShortForm|DefaultSize, { WordReg, 0, 0 } }, {"push", 1, 0xff, 6, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem, 0, 0 } }, {"push", 1, 0x6a, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm8S, 0, 0} }, {"push", 1, 0x68, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16|Imm32, 0, 0} }, -{"push", 1, 0x06, X, 0|CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, +{"push", 1, 0x06, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, {"push", 1, 0x0fa0, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, /* In 64bit mode, the operand size is implicitly 64bit. */ -{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, -{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, -{"push", 1, 0x6a, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, -{"push", 1, 0x68, X, Cpu186|Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, -{"push", 1, 0x06, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, -{"push", 1, 0x0fa0, X, Cpu386|Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, +{"push", 1, 0x50, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, +{"push", 1, 0xff, 6, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, +{"push", 1, 0x6a, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm8S, 0, 0} }, +{"push", 1, 0x68, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm32S|Imm16, 0, 0} }, +{"push", 1, 0x0fa0, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, {"pusha", 0, 0x60, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, @@ -165,9 +167,8 @@ static const template i386_optab[] = { {"pop", 1, 0x07, X, CpuNo64, wl_Suf|Seg2ShortForm|DefaultSize, { SReg2, 0, 0 } }, {"pop", 1, 0x0fa1, X, Cpu386|CpuNo64, wl_Suf|Seg3ShortForm|DefaultSize, { SReg3, 0, 0 } }, /* In 64bit mode, the operand size is implicitly 64bit. */ -{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { WordReg, 0, 0 } }, -{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { WordReg|WordMem, 0, 0 } }, -{"pop", 1, 0x07, X, Cpu64, wq_Suf|Seg2ShortForm|DefaultSize|NoRex64, { SReg2, 0, 0 } }, +{"pop", 1, 0x58, X, Cpu64, wq_Suf|ShortForm|DefaultSize|NoRex64, { Reg16|Reg64, 0, 0 } }, +{"pop", 1, 0x8f, 0, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem, 0, 0 } }, {"pop", 1, 0x0fa1, X, Cpu64, wq_Suf|Seg3ShortForm|DefaultSize|NoRex64, { SReg3, 0, 0 } }, {"popa", 0, 0x61, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0 } }, @@ -175,14 +176,24 @@ static const template i386_optab[] = { /* Exchange instructions. xchg commutes: we allow both operand orders. - In the 64bit code, xchg eax, eax is reused for new nop instruction. - */ + In the 64bit code, xchg eax, eax is reused for new nop instruction. */ +#if 0 /* While the two entries that are disabled generate shorter code + for xchg eax, reg (on x86_64), the special case xchg eax, eax + does not get handled correctly - it degenerates into nop, but + that way the side effect of zero-extending eax to rax is lost. */ {"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { WordReg, Acc, 0 } }, {"xchg", 2, 0x90, X, 0, wlq_Suf|ShortForm, { Acc, WordReg, 0 } }, +#else +{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { WordReg, Acc, 0 } }, +{"xchg", 2, 0x90, X, CpuNo64, wl_Suf|ShortForm, { Acc, WordReg, 0 } }, +{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Reg16|Reg64, Acc, 0 } }, +{"xchg", 2, 0x90, X, Cpu64, wq_Suf|ShortForm, { Acc, Reg16|Reg64, 0 } }, +#endif {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"xchg", 2, 0x86, X, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, Reg, 0 } }, /* In/out from ports. */ +/* XXX should reject %rax */ {"in", 2, 0xe4, X, 0, bwl_Suf|W, { Imm8, Acc, 0 } }, {"in", 2, 0xec, X, 0, bwl_Suf|W, { InOutPortReg, Acc, 0 } }, {"in", 1, 0xe4, X, 0, bwl_Suf|W, { Imm8, 0, 0 } }, @@ -196,11 +207,11 @@ static const template i386_optab[] = { {"lea", 2, 0x8d, X, 0, wlq_Suf|Modrm, { WordMem, WordReg, 0 } }, /* Load segment registers from memory. */ -{"lds", 2, 0xc5, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"les", 2, 0xc4, X, CpuNo64, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lfs", 2, 0x0fb4, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lgs", 2, 0x0fb5, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, -{"lss", 2, 0x0fb2, X, Cpu386, wlq_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lds", 2, 0xc5, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"les", 2, 0xc4, X, CpuNo64, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lfs", 2, 0x0fb4, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lgs", 2, 0x0fb5, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, +{"lss", 2, 0x0fb2, X, Cpu386, wl_Suf|Modrm, { WordMem, WordReg, 0} }, /* Flags register instructions. */ {"clc", 0, 0xf8, X, 0, NoSuf, { 0, 0, 0} }, @@ -208,11 +219,11 @@ static const template i386_optab[] = { {"cli", 0, 0xfa, X, 0, NoSuf, { 0, 0, 0} }, {"clts", 0, 0x0f06, X, Cpu286, NoSuf, { 0, 0, 0} }, {"cmc", 0, 0xf5, X, 0, NoSuf, { 0, 0, 0} }, -{"lahf", 0, 0x9f, X, CpuNo64,NoSuf, { 0, 0, 0} }, -{"sahf", 0, 0x9e, X, CpuNo64,NoSuf, { 0, 0, 0} }, -{"pushf", 0, 0x9c, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"lahf", 0, 0x9f, X, 0, NoSuf, { 0, 0, 0} }, +{"sahf", 0, 0x9e, X, 0, NoSuf, { 0, 0, 0} }, +{"pushf", 0, 0x9c, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, {"pushf", 0, 0x9c, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"popf", 0, 0x9d, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"popf", 0, 0x9d, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, {"popf", 0, 0x9d, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, {"stc", 0, 0xf9, X, 0, NoSuf, { 0, 0, 0} }, {"std", 0, 0xfd, X, 0, NoSuf, { 0, 0, 0} }, @@ -276,14 +287,14 @@ static const template i386_optab[] = { {"neg", 1, 0xf6, 3, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, {"not", 1, 0xf6, 2, 0, bwlq_Suf|W|Modrm, { Reg|AnyMem, 0, 0} }, -{"aaa", 0, 0x37, X, 0, NoSuf, { 0, 0, 0} }, -{"aas", 0, 0x3f, X, 0, NoSuf, { 0, 0, 0} }, -{"daa", 0, 0x27, X, 0, NoSuf, { 0, 0, 0} }, -{"das", 0, 0x2f, X, 0, NoSuf, { 0, 0, 0} }, -{"aad", 0, 0xd50a, X, 0, NoSuf, { 0, 0, 0} }, -{"aad", 1, 0xd5, X, 0, NoSuf, { Imm8S, 0, 0} }, -{"aam", 0, 0xd40a, X, 0, NoSuf, { 0, 0, 0} }, -{"aam", 1, 0xd4, X, 0, NoSuf, { Imm8S, 0, 0} }, +{"aaa", 0, 0x37, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aas", 0, 0x3f, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"daa", 0, 0x27, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"das", 0, 0x2f, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aad", 0, 0xd50a, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aad", 1, 0xd5, X, CpuNo64, NoSuf, { Imm8S, 0, 0} }, +{"aam", 0, 0xd40a, X, CpuNo64, NoSuf, { 0, 0, 0} }, +{"aam", 1, 0xd4, X, CpuNo64, NoSuf, { Imm8S, 0, 0} }, /* Conversion insns. */ /* Intel naming */ @@ -370,37 +381,38 @@ static const template i386_optab[] = { {"shrd", 2, 0x0fad, X, Cpu386, wlq_Suf|Modrm, { WordReg, WordReg|WordMem, 0} }, /* Control transfer instructions. */ -{"call", 1, 0xe8, X, 0, wlq_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xe8, X, CpuNo64, wl_Suf|JumpDword|DefaultSize, { Disp16|Disp32, 0, 0} }, +{"call", 1, 0xe8, X, Cpu64, wq_Suf|JumpDword|DefaultSize|NoRex64, { Disp16|Disp32, 0, 0} }, {"call", 1, 0xff, 2, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64,{ WordReg|WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xff, 2, Cpu64, wq_Suf|Modrm|DefaultSize|NoRex64, { Reg16|Reg64|WordMem|LLongMem|JumpAbsolute, 0, 0} }, /* Intel Syntax */ -{"call", 2, 0x9a, X, CpuNo64,wlq_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, +{"call", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, /* Intel Syntax */ -{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, { WordMem, 0, 0} }, -{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, { Imm16, Imm16|Imm32, 0} }, -{"lcall", 1, 0xff, 3, CpuNo64, wl_Suf|Modrm|DefaultSize, { WordMem|JumpAbsolute, 0, 0} }, -{"lcall", 1, 0xff, 3, Cpu64, q_Suf|Modrm|DefaultSize|NoRex64,{ WordMem|JumpAbsolute, 0, 0} }, +{"call", 1, 0xff, 3, 0, x_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, +{"lcall", 2, 0x9a, X, CpuNo64, wl_Suf|JumpInterSegment|DefaultSize, {Imm16, Imm16|Imm32, 0} }, +{"lcall", 1, 0xff, 3, 0, wl_Suf|Modrm|DefaultSize, {WordMem|JumpAbsolute, 0, 0} }, #define JUMP_PC_RELATIVE 0xeb -{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp, 0, 0} }, +{"jmp", 1, 0xeb, X, 0, NoSuf|Jump, { Disp,0, 0} }, {"jmp", 1, 0xff, 4, CpuNo64, wl_Suf|Modrm, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { WordReg|WordMem|JumpAbsolute, 0, 0} }, -/* Intel Syntax */ +{"jmp", 1, 0xff, 4, Cpu64, wq_Suf|Modrm|NoRex64, { Reg16|Reg64|ShortMem|LLongMem|JumpAbsolute, 0, 0} }, +/* Intel Syntax. */ {"jmp", 2, 0xea, X, CpuNo64,wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -/* Intel Syntax */ -{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem, 0, 0} }, -{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, -{"ljmp", 1, 0xff, 5, CpuNo64, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, -{"ljmp", 1, 0xff, 5, Cpu64, q_Suf|Modrm|NoRex64, { WordMem|JumpAbsolute, 0, 0} }, - -{"ret", 0, 0xc3, X, CpuNo64,wlq_Suf|DefaultSize, { 0, 0, 0} }, -{"ret", 1, 0xc2, X, CpuNo64,wlq_Suf|DefaultSize, { Imm16, 0, 0} }, -{"ret", 0, 0xc3, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, -{"ret", 1, 0xc2, X, Cpu64, q_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, +/* Intel Syntax. */ +{"jmp", 1, 0xff, 5, 0, x_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, +{"ljmp", 2, 0xea, X, CpuNo64, wl_Suf|JumpInterSegment, { Imm16, Imm16|Imm32, 0} }, +{"ljmp", 1, 0xff, 5, 0, wl_Suf|Modrm, { WordMem|JumpAbsolute, 0, 0} }, + +{"ret", 0, 0xc3, X, CpuNo64,wl_Suf|DefaultSize, { 0, 0, 0} }, +{"ret", 1, 0xc2, X, CpuNo64,wl_Suf|DefaultSize, { Imm16, 0, 0} }, +{"ret", 0, 0xc3, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ 0, 0, 0} }, +{"ret", 1, 0xc2, X, Cpu64, wq_Suf|DefaultSize|NoRex64,{ Imm16, 0, 0} }, {"lret", 0, 0xcb, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, {"lret", 1, 0xca, X, 0, wlq_Suf|DefaultSize, { Imm16, 0, 0} }, -{"enter", 2, 0xc8, X, Cpu186, wlq_Suf|DefaultSize, { Imm16, Imm8, 0} }, -{"leave", 0, 0xc9, X, Cpu186, wlq_Suf|DefaultSize, { 0, 0, 0} }, +{"enter", 2, 0xc8, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { Imm16, Imm8, 0} }, +{"enter", 2, 0xc8, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { Imm16, Imm8, 0} }, +{"leave", 0, 0xc9, X, Cpu186|CpuNo64, wl_Suf|DefaultSize, { 0, 0, 0} }, +{"leave", 0, 0xc9, X, Cpu64, wq_Suf|DefaultSize|NoRex64, { 0, 0, 0} }, /* Conditional jumps. */ {"jo", 1, 0x70, X, 0, NoSuf|Jump, { Disp, 0, 0} }, @@ -536,33 +548,37 @@ static const template i386_optab[] = { /* Interrupts & op. sys insns. */ /* See gas/config/tc-i386.c for conversion of 'int $3' into the special int 3 insn. */ -#define INT_OPCODE 0xcd +#define INT_OPCODE 0xcd #define INT3_OPCODE 0xcc {"int", 1, 0xcd, X, 0, NoSuf, { Imm8, 0, 0} }, {"int3", 0, 0xcc, X, 0, NoSuf, { 0, 0, 0} }, -{"into", 0, 0xce, X, 0, NoSuf, { 0, 0, 0} }, +{"into", 0, 0xce, X, CpuNo64, NoSuf, { 0, 0, 0} }, {"iret", 0, 0xcf, X, 0, wlq_Suf|DefaultSize, { 0, 0, 0} }, /* i386sl, i486sl, later 486, and Pentium. */ {"rsm", 0, 0x0faa, X, Cpu386, NoSuf, { 0, 0, 0} }, -{"bound", 2, 0x62, X, Cpu186, wlq_Suf|Modrm, { WordReg, WordMem, 0} }, +{"bound", 2, 0x62, X, Cpu186|CpuNo64, wl_Suf|Modrm, { WordReg, WordMem, 0} }, {"hlt", 0, 0xf4, X, 0, NoSuf, { 0, 0, 0} }, /* nop is actually 'xchgl %eax, %eax'. */ {"nop", 0, 0x90, X, 0, NoSuf, { 0, 0, 0} }, /* Protection control. */ -{"arpl", 2, 0x63, X, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, +{"arpl", 2, 0x63, X, Cpu286|CpuNo64, w_Suf|Modrm|IgnoreSize,{ Reg16, Reg16|ShortMem, 0} }, {"lar", 2, 0x0f02, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, -{"lgdt", 1, 0x0f01, 2, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"lidt", 1, 0x0f01, 3, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, +{"lgdt", 1, 0x0f01, 2, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"lgdt", 1, 0x0f01, 2, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"lidt", 1, 0x0f01, 3, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"lidt", 1, 0x0f01, 3, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, {"lldt", 1, 0x0f00, 2, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"lmsw", 1, 0x0f01, 6, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, {"lsl", 2, 0x0f03, X, Cpu286, wlq_Suf|Modrm, { WordReg|WordMem, WordReg, 0} }, {"ltr", 1, 0x0f00, 3, Cpu286, w_Suf|Modrm|IgnoreSize,{ Reg16|ShortMem, 0, 0} }, -{"sgdt", 1, 0x0f01, 0, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, -{"sidt", 1, 0x0f01, 1, Cpu286, wlq_Suf|Modrm, { WordMem, 0, 0} }, +{"sgdt", 1, 0x0f01, 0, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"sgdt", 1, 0x0f01, 0, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, Cpu286|CpuNo64, wl_Suf|Modrm, { WordMem, 0, 0} }, +{"sidt", 1, 0x0f01, 1, Cpu64, q_Suf|Modrm|NoRex64, { LLongMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, {"sldt", 1, 0x0f00, 0, Cpu286, w_Suf|Modrm|IgnoreSize,{ ShortMem, 0, 0} }, {"smsw", 1, 0x0f01, 4, Cpu286, wlq_Suf|Modrm, { WordReg|InvMem, 0, 0} }, @@ -577,37 +593,33 @@ static const template i386_optab[] = { /* load */ {"fld", 1, 0xd9c0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fld", 1, 0xd9, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fld", 1, 0xd9, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fld", 1, 0xd9c0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, /* Intel Syntax */ {"fld", 1, 0xdb, 5, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fild", 1, 0xdf, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -/* Intel Syntax */ -{"fildd", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fildq", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fild", 1, 0xdf, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fild", 1, 0xdf, 5, 0, q_FP|Modrm, { LLongMem, 0, 0} }, {"fildll", 1, 0xdf, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, {"fldt", 1, 0xdb, 5, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbld", 1, 0xdf, 4, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fbld", 1, 0xdf, 4, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, /* store (no pop) */ {"fst", 1, 0xddd0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fst", 1, 0xd9, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"fist", 1, 0xdf, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fst", 1, 0xd9, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fst", 1, 0xddd0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, +{"fist", 1, 0xdf, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, /* store (with pop) */ {"fstp", 1, 0xddd8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, -{"fstp", 1, 0xd9, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, +{"fstp", 1, 0xd9, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fstp", 1, 0xddd8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, /* Intel Syntax */ {"fstp", 1, 0xdb, 7, 0, x_FP|Modrm, { LLongMem, 0, 0} }, -{"fistp", 1, 0xdf, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -/* Intel Syntax */ -{"fistpd", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fistpq", 1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fistp", 1, 0xdf, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fistp", 1, 0xdf, 7, 0, q_FP|Modrm, { LLongMem, 0, 0} }, {"fistpll",1, 0xdf, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, {"fstpt", 1, 0xdb, 7, 0, FP|Modrm, { LLongMem, 0, 0} }, -{"fbstp", 1, 0xdf, 6, 0, FP|Modrm, { LLongMem, 0, 0} }, +{"fbstp", 1, 0xdf, 6, 0, x_Suf|Modrm, { LLongMem, 0, 0} }, /* exchange %st<n> with %st0 */ {"fxch", 1, 0xd9c8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, @@ -618,17 +630,17 @@ static const template i386_optab[] = { {"fcom", 1, 0xd8d0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fcom %st(1) */ {"fcom", 0, 0xd8d1, X, 0, FP, { 0, 0, 0} }, -{"fcom", 1, 0xd8, 2, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"ficom", 1, 0xde, 2, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fcom", 1, 0xd8, 2, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fcom", 1, 0xd8d0, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, +{"ficom", 1, 0xde, 2, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, /* comparison (with pop) */ {"fcomp", 1, 0xd8d8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* alias for fcomp %st(1) */ {"fcomp", 0, 0xd8d9, X, 0, FP, { 0, 0, 0} }, -{"fcomp", 1, 0xd8, 3, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|Ugh, { FloatReg, 0, 0} }, -{"ficomp", 1, 0xde, 3, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fcomp", 1, 0xd8, 3, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fcomp", 1, 0xd8d8, X, 0, l_FP|ShortForm|IgnoreSize|Ugh, { FloatReg, 0, 0} }, +{"ficomp", 1, 0xde, 3, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, {"fcompp", 0, 0xded9, X, 0, FP, { 0, 0, 0} }, /* unordered comparison (with pop) */ @@ -652,7 +664,7 @@ static const template i386_optab[] = { {"fldln2", 0, 0xd9ed, X, 0, FP, { 0, 0, 0} }, {"fldz", 0, 0xd9ee, X, 0, FP, { 0, 0, 0} }, -/* arithmetic */ +/* Arithmetic. */ /* add */ {"fadd", 2, 0xd8c0, X, 0, FP|ShortForm|FloatD, { FloatReg, FloatAcc, 0} }, @@ -662,8 +674,8 @@ static const template i386_optab[] = { /* alias for faddp */ {"fadd", 0, 0xdec1, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fadd", 1, 0xd8, 0, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fiadd", 1, 0xde, 0, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fadd", 1, 0xd8, 0, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fiadd", 1, 0xde, 0, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, {"faddp", 2, 0xdec0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"faddp", 1, 0xdec0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, @@ -678,8 +690,8 @@ static const template i386_optab[] = { /* alias for fsubp */ {"fsub", 0, 0xdee1, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fsub", 1, 0xd8, 4, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisub", 1, 0xde, 4, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fsub", 1, 0xd8, 4, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisub", 1, 0xde, 4, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT {"fsubp", 2, 0xdee0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, @@ -701,8 +713,8 @@ static const template i386_optab[] = { /* alias for fsubrp */ {"fsubr", 0, 0xdee9, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fsubr", 1, 0xd8, 5, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fisubr", 1, 0xde, 5, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fsubr", 1, 0xd8, 5, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fisubr", 1, 0xde, 5, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT {"fsubrp", 2, 0xdee8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, @@ -724,8 +736,8 @@ static const template i386_optab[] = { /* alias for fmulp */ {"fmul", 0, 0xdec9, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fmul", 1, 0xd8, 1, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fimul", 1, 0xde, 1, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fmul", 1, 0xd8, 1, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fimul", 1, 0xde, 1, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, {"fmulp", 2, 0xdec8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, {"fmulp", 1, 0xdec8, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, @@ -739,8 +751,8 @@ static const template i386_optab[] = { /* alias for fdivp */ {"fdiv", 0, 0xdef1, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fdiv", 1, 0xd8, 6, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidiv", 1, 0xde, 6, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fdiv", 1, 0xd8, 6, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidiv", 1, 0xde, 6, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT {"fdivp", 2, 0xdef0, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, @@ -762,8 +774,8 @@ static const template i386_optab[] = { /* alias for fdivrp */ {"fdivr", 0, 0xdef9, X, 0, FP|Ugh, { 0, 0, 0} }, #endif -{"fdivr", 1, 0xd8, 7, 0, sl_FP|FloatMF|Modrm, { LongMem|LLongMem, 0, 0} }, -{"fidivr", 1, 0xde, 7, 0, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fdivr", 1, 0xd8, 7, 0, sl_FP|Modrm, { LongMem|LLongMem, 0, 0} }, +{"fidivr", 1, 0xde, 7, 0, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, #if SYSV386_COMPAT {"fdivrp", 2, 0xdef8, X, 0, FP|ShortForm, { FloatAcc, FloatReg, 0} }, @@ -800,24 +812,26 @@ static const template i386_optab[] = { /* processor control */ {"fninit", 0, 0xdbe3, X, 0, FP, { 0, 0, 0} }, {"finit", 0, 0xdbe3, X, 0, FP|FWait, { 0, 0, 0} }, -{"fldcw", 1, 0xd9, 5, 0, FP|Modrm, { ShortMem, 0, 0} }, -{"fnstcw", 1, 0xd9, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, -{"fstcw", 1, 0xd9, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, -{"fnstsw", 1, 0xdfe0, X, 0, FP, { Acc, 0, 0} }, -{"fnstsw", 1, 0xdd, 7, 0, FP|Modrm, { ShortMem, 0, 0} }, +{"fldcw", 1, 0xd9, 5, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, +{"fnstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, +{"fstcw", 1, 0xd9, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, +/* XXX should reject %al, %eax, and %rax */ +{"fnstsw", 1, 0xdfe0, X, 0, FP|IgnoreSize, { Acc, 0, 0} }, +{"fnstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|Modrm, { ShortMem, 0, 0} }, {"fnstsw", 0, 0xdfe0, X, 0, FP, { 0, 0, 0} }, -{"fstsw", 1, 0xdfe0, X, 0, FP|FWait, { Acc, 0, 0} }, -{"fstsw", 1, 0xdd, 7, 0, FP|FWait|Modrm, { ShortMem, 0, 0} }, +/* XXX should reject %al, %eax, and %rax */ +{"fstsw", 1, 0xdfe0, X, 0, FP|FWait|IgnoreSize, { Acc, 0, 0} }, +{"fstsw", 1, 0xdd, 7, 0, w_Suf|FloatMF|FWait|Modrm, { ShortMem, 0, 0} }, {"fstsw", 0, 0xdfe0, X, 0, FP|FWait, { 0, 0, 0} }, {"fnclex", 0, 0xdbe2, X, 0, FP, { 0, 0, 0} }, {"fclex", 0, 0xdbe2, X, 0, FP|FWait, { 0, 0, 0} }, /* Short forms of fldenv, fstenv use data size prefix. */ -{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, -{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, -{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm, { LLongMem, 0, 0} }, -{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm, { LLongMem, 0, 0} }, +{"fnstenv",1, 0xd9, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, +{"fstenv", 1, 0xd9, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, +{"fldenv", 1, 0xd9, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, +{"fnsave", 1, 0xdd, 6, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, +{"fsave", 1, 0xdd, 6, 0, sl_Suf|FWait|Modrm|DefaultSize, { LLongMem, 0, 0} }, +{"frstor", 1, 0xdd, 4, 0, sl_Suf|Modrm|DefaultSize, { LLongMem, 0, 0} }, {"ffree", 1, 0xddc0, X, 0, FP|ShortForm, { FloatReg, 0, 0} }, /* P6:free st(i), pop st */ @@ -829,30 +843,30 @@ static const template i386_optab[] = { /* Opcode prefixes; we allow them as separate insns too. */ #define ADDR_PREFIX_OPCODE 0x67 -{"addr16", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"addr32", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"aword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"adword", 0, 0x67, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"addr16", 0, 0x67, X, Cpu386|CpuNo64, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"addr32", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"aword", 0, 0x67, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"adword", 0, 0x67, X, Cpu386,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define DATA_PREFIX_OPCODE 0x66 -{"data16", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"data32", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, -{"word", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, -{"dword", 0, 0x66, X, Cpu386, NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"data16", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"data32", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, +{"word", 0, 0x66, X, Cpu386,NoSuf|IsPrefix|Size16|IgnoreSize, { 0, 0, 0} }, +{"dword", 0, 0x66, X, Cpu386|CpuNo64,NoSuf|IsPrefix|Size32|IgnoreSize, { 0, 0, 0} }, #define LOCK_PREFIX_OPCODE 0xf0 {"lock", 0, 0xf0, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, {"wait", 0, 0x9b, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define CS_PREFIX_OPCODE 0x2e -{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"cs", 0, 0x2e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define DS_PREFIX_OPCODE 0x3e -{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"ds", 0, 0x3e, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, #define ES_PREFIX_OPCODE 0x26 -{"es", 0, 0x26, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"es", 0, 0x26, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, #define FS_PREFIX_OPCODE 0x64 {"fs", 0, 0x64, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define GS_PREFIX_OPCODE 0x65 {"gs", 0, 0x65, X, Cpu386, NoSuf|IsPrefix, { 0, 0, 0} }, #define SS_PREFIX_OPCODE 0x36 -{"ss", 0, 0x36, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, +{"ss", 0, 0x36, X, CpuNo64, NoSuf|IsPrefix, { 0, 0, 0} }, #define REPNE_PREFIX_OPCODE 0xf2 #define REPE_PREFIX_OPCODE 0xf3 {"rep", 0, 0xf3, X, 0, NoSuf|IsPrefix, { 0, 0, 0} }, @@ -884,7 +898,7 @@ static const template i386_optab[] = { {"cmpxchg", 2, 0x0fb0, X, Cpu486, bwlq_Suf|W|Modrm, { Reg, Reg|AnyMem, 0 } }, {"invd", 0, 0x0f08, X, Cpu486, NoSuf, { 0, 0, 0} }, {"wbinvd", 0, 0x0f09, X, Cpu486, NoSuf, { 0, 0, 0} }, -{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm, { AnyMem, 0, 0} }, +{"invlpg", 1, 0x0f01, 7, Cpu486, NoSuf|Modrm|IgnoreSize, { AnyMem, 0, 0} }, /* 586 and late 486 extensions. */ {"cpuid", 0, 0x0fa2, X, Cpu486, NoSuf, { 0, 0, 0} }, @@ -893,13 +907,13 @@ static const template i386_optab[] = { {"wrmsr", 0, 0x0f30, X, Cpu586, NoSuf, { 0, 0, 0} }, {"rdtsc", 0, 0x0f31, X, Cpu586, NoSuf, { 0, 0, 0} }, {"rdmsr", 0, 0x0f32, X, Cpu586, NoSuf, { 0, 0, 0} }, -{"cmpxchg8b",1,0x0fc7, 1, Cpu586, NoSuf|Modrm, { LLongMem, 0, 0} }, +{"cmpxchg8b",1,0x0fc7, 1, Cpu586, q_Suf|Modrm, { LLongMem, 0, 0} }, /* Pentium II/Pentium Pro extensions. */ {"sysenter",0, 0x0f34, X, Cpu686, NoSuf, { 0, 0, 0} }, {"sysexit", 0, 0x0f35, X, Cpu686, NoSuf, { 0, 0, 0} }, -{"fxsave", 1, 0x0fae, 0, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, -{"fxrstor", 1, 0x0fae, 1, Cpu686, FP|Modrm, { LLongMem, 0, 0} }, +{"fxsave", 1, 0x0fae, 0, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, +{"fxrstor", 1, 0x0fae, 1, Cpu686, q_Suf|Modrm, { LLongMem, 0, 0} }, {"rdpmc", 0, 0x0f33, X, Cpu686, NoSuf, { 0, 0, 0} }, /* official undefined instr. */ {"ud2", 0, 0x0f0b, X, Cpu686, NoSuf, { 0, 0, 0} }, @@ -967,30 +981,25 @@ static const template i386_optab[] = { /* Pentium4 extensions. */ -{"movnti", 2, 0x0fc3, X, CpuP4, FP|Modrm, { WordReg, WordMem, 0 } }, -{"clflush", 1, 0x0fae, 7, CpuP4, FP|Modrm, { ByteMem, 0, 0 } }, -{"lfence", 0, 0x0fae, 0xe8, CpuP4, FP|ImmExt, { 0, 0, 0 } }, -{"mfence", 0, 0x0fae, 0xf0, CpuP4, FP|ImmExt, { 0, 0, 0 } }, -{"pause", 0, 0xf390, X, CpuP4, FP, { 0, 0, 0 } }, +{"movnti", 2, 0x0fc3, X, CpuP4, wlq_Suf|Modrm, { WordReg, WordMem, 0 } }, +{"clflush", 1, 0x0fae, 7, CpuP4, NoSuf|Modrm|IgnoreSize, { ByteMem, 0, 0 } }, +{"lfence", 0, 0x0fae, 0xe8, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, +{"mfence", 0, 0x0fae, 0xf0, CpuP4, NoSuf|ImmExt, { 0, 0, 0 } }, +{"pause", 0, 0xf390, X, CpuP4, NoSuf, { 0, 0, 0 } }, /* MMX/SSE2 instructions. */ -{"emms", 0, 0x0f77, X, CpuMMX, FP, { 0, 0, 0 } }, -{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg32|LongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg32|LongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg32|LLongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg32|LLongMem, 0 } }, -/* Real MMX instructions. */ -{"movd", 2, 0x0f6e, X, CpuMMX, FP|Modrm, { Reg64|LLongMem, RegMMX, 0 } }, -{"movd", 2, 0x0f7e, X, CpuMMX, FP|Modrm, { RegMMX, Reg64|LLongMem, 0 } }, -{"movd", 2, 0x660f6e,X,CpuSSE2,FP|Modrm, { Reg64|LLongMem, RegXMM, 0 } }, -{"movd", 2, 0x660f7e,X,CpuSSE2,FP|Modrm, { RegXMM, Reg64|LLongMem, 0 } }, +{"emms", 0, 0x0f77, X, CpuMMX, NoSuf, { 0, 0, 0 } }, +{"movd", 2, 0x0f6e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LongMem, RegMMX, 0 } }, +{"movd", 2, 0x0f7e, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, Reg32|Reg64|LongMem, 0 } }, +{"movd", 2, 0x660f6e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Reg32|Reg64|LLongMem, RegXMM, 0 } }, +{"movd", 2, 0x660f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, Reg32|Reg64|LLongMem, 0 } }, /* In the 64bit mode the short form mov immediate is redefined to have 64bit displacement value. */ -{"movq", 2, 0x0f6f, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"movq", 2, 0x0f7f, X, CpuMMX, FP|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, -{"movq", 2, 0xf30f7e,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movq", 2, 0x660fd6,X,CpuSSE2,FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movq", 2, 0x0f6f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"movq", 2, 0x0f7f, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX, RegMMX|LongMem, 0 } }, +{"movq", 2, 0xf30f7e,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movq", 2, 0x660fd6,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, {"movq", 2, 0x88, X, Cpu64, NoSuf|D|W|Modrm|Size64,{ Reg64, Reg64|AnyMem, 0 } }, {"movq", 2, 0xc6, 0, Cpu64, NoSuf|W|Modrm|Size64, { Imm32S, Reg64|WordMem, 0 } }, {"movq", 2, 0xb0, X, Cpu64, NoSuf|W|ShortForm|Size64,{ Imm64, Reg64, 0 } }, @@ -998,377 +1007,381 @@ static const template i386_optab[] = { mode they are 64bit.*/ {"movq", 2, 0x0f20, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Control, Reg64|InvMem, 0} }, {"movq", 2, 0x0f21, X, Cpu64, NoSuf|D|Modrm|IgnoreSize|NoRex64|Size64,{ Debug, Reg64|InvMem, 0} }, -{"packssdw", 2, 0x0f6b, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packssdw", 2, 0x660f6b,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packsswb", 2, 0x0f63, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packsswb", 2, 0x660f63,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"packuswb", 2, 0x0f67, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"packuswb", 2, 0x660f67,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddb", 2, 0x0ffc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddb", 2, 0x660ffc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddw", 2, 0x0ffd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddw", 2, 0x660ffd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddd", 2, 0x0ffe, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddd", 2, 0x660ffe,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddq", 2, 0x0fd4, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"paddq", 2, 0x660fd4,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsb", 2, 0x0fec, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsb", 2, 0x660fec,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddsw", 2, 0x0fed, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddsw", 2, 0x660fed,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusb", 2, 0x0fdc, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusb", 2, 0x660fdc,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"paddusw", 2, 0x0fdd, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"paddusw", 2, 0x660fdd,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pand", 2, 0x0fdb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pand", 2, 0x660fdb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pandn", 2, 0x0fdf, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pandn", 2, 0x660fdf,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqb", 2, 0x0f74, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqw", 2, 0x0f75, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpeqd", 2, 0x0f76, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtb", 2, 0x0f64, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtw", 2, 0x0f65, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pcmpgtd", 2, 0x0f66, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaddwd", 2, 0x0ff5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmulhw", 2, 0x0fe5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhw", 2, 0x660fe5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmullw", 2, 0x0fd5, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmullw", 2, 0x660fd5,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"por", 2, 0x0feb, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"por", 2, 0x660feb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0ff1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllw", 2, 0x660ff1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllw", 2, 0x0f71, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psllw", 2, 0x660f71,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"pslld", 2, 0x0ff2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pslld", 2, 0x660ff2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pslld", 2, 0x0f72, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"pslld", 2, 0x660f72,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psllq", 2, 0x0ff3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psllq", 2, 0x660ff3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psllq", 2, 0x0f73, 6, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psllq", 2, 0x660f73,6,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psraw", 2, 0x0fe1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psraw", 2, 0x660fe1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psraw", 2, 0x0f71, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psraw", 2, 0x660f71,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrad", 2, 0x0fe2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrad", 2, 0x660fe2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrad", 2, 0x0f72, 4, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrad", 2, 0x660f72,4,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlw", 2, 0x0fd1, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlw", 2, 0x660fd1,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlw", 2, 0x0f71, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlw", 2, 0x660f71,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrld", 2, 0x0fd2, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrld", 2, 0x660fd2,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrld", 2, 0x0f72, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrld", 2, 0x660f72,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrlq", 2, 0x0fd3, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psrlq", 2, 0x660fd3,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psrlq", 2, 0x0f73, 2, CpuMMX, FP|Modrm, { Imm8, RegMMX, 0 } }, -{"psrlq", 2, 0x660f73,2,CpuSSE2,FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psubb", 2, 0x0ff8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubb", 2, 0x660ff8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubw", 2, 0x0ff9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubw", 2, 0x660ff9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubd", 2, 0x0ffa, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubd", 2, 0x660ffa,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubq", 2, 0x0ffb, X, CpuMMX, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psubq", 2, 0x660ffb,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsb", 2, 0x0fe8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsb", 2, 0x660fe8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubsw", 2, 0x0fe9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubsw", 2, 0x660fe9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusb", 2, 0x0fd8, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusb", 2, 0x660fd8,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"psubusw", 2, 0x0fd9, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"psubusw", 2, 0x660fd9,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhbw",2, 0x0f68, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhbw",2, 0x660f68,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhwd",2, 0x0f69, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhwd",2, 0x660f69,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckhdq",2, 0x0f6a, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckhdq",2, 0x660f6a,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklbw",2, 0x0f60, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklbw",2, 0x660f60,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklwd",2, 0x0f61, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpcklwd",2, 0x660f61,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpckldq",2, 0x0f62, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"punpckldq",2, 0x660f62,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pxor", 2, 0x0fef, X, CpuMMX, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pxor", 2, 0x660fef,X,CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +/* Real MMX instructions. */ +{"packssdw", 2, 0x0f6b, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packssdw", 2, 0x660f6b,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"packsswb", 2, 0x0f63, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packsswb", 2, 0x660f63,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"packuswb", 2, 0x0f67, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"packuswb", 2, 0x660f67,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddb", 2, 0x0ffc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddb", 2, 0x660ffc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddw", 2, 0x0ffd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddw", 2, 0x660ffd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddd", 2, 0x0ffe, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddd", 2, 0x660ffe,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddq", 2, 0x0fd4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"paddq", 2, 0x660fd4,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddsb", 2, 0x0fec, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsb", 2, 0x660fec,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddsw", 2, 0x0fed, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddsw", 2, 0x660fed,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddusb", 2, 0x0fdc, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusb", 2, 0x660fdc,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"paddusw", 2, 0x0fdd, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"paddusw", 2, 0x660fdd,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pand", 2, 0x0fdb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pand", 2, 0x660fdb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pandn", 2, 0x0fdf, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pandn", 2, 0x660fdf,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqb", 2, 0x0f74, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqb", 2, 0x660f74,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqw", 2, 0x0f75, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqw", 2, 0x660f75,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpeqd", 2, 0x0f76, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpeqd", 2, 0x660f76,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtb", 2, 0x0f64, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtb", 2, 0x660f64,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtw", 2, 0x0f65, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtw", 2, 0x660f65,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pcmpgtd", 2, 0x0f66, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pcmpgtd", 2, 0x660f66,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmaddwd", 2, 0x0ff5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmaddwd", 2, 0x660ff5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmulhw", 2, 0x0fe5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhw", 2, 0x660fe5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmullw", 2, 0x0fd5, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmullw", 2, 0x660fd5,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"por", 2, 0x0feb, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"por", 2, 0x660feb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllw", 2, 0x0ff1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllw", 2, 0x660ff1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllw", 2, 0x0f71, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psllw", 2, 0x660f71,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"pslld", 2, 0x0ff2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pslld", 2, 0x660ff2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pslld", 2, 0x0f72, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"pslld", 2, 0x660f72,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psllq", 2, 0x0ff3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psllq", 2, 0x660ff3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psllq", 2, 0x0f73, 6, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psllq", 2, 0x660f73,6,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psraw", 2, 0x0fe1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psraw", 2, 0x660fe1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psraw", 2, 0x0f71, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psraw", 2, 0x660f71,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psrad", 2, 0x0fe2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrad", 2, 0x660fe2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrad", 2, 0x0f72, 4, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psrad", 2, 0x660f72,4,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psrlw", 2, 0x0fd1, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlw", 2, 0x660fd1,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrlw", 2, 0x0f71, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlw", 2, 0x660f71,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psrld", 2, 0x0fd2, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrld", 2, 0x660fd2,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrld", 2, 0x0f72, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psrld", 2, 0x660f72,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psrlq", 2, 0x0fd3, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psrlq", 2, 0x660fd3,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psrlq", 2, 0x0f73, 2, CpuMMX, NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX, 0 } }, +{"psrlq", 2, 0x660f73,2,CpuSSE2,NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psubb", 2, 0x0ff8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubb", 2, 0x660ff8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubw", 2, 0x0ff9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubw", 2, 0x660ff9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubd", 2, 0x0ffa, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubd", 2, 0x660ffa,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubq", 2, 0x0ffb, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psubq", 2, 0x660ffb,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubsb", 2, 0x0fe8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsb", 2, 0x660fe8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubsw", 2, 0x0fe9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubsw", 2, 0x660fe9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubusb", 2, 0x0fd8, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusb", 2, 0x660fd8,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"psubusw", 2, 0x0fd9, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"psubusw", 2, 0x660fd9,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhbw",2, 0x0f68, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhbw",2, 0x660f68,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhwd",2, 0x0f69, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhwd",2, 0x660f69,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckhdq",2, 0x0f6a, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckhdq",2, 0x660f6a,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklbw",2, 0x0f60, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklbw",2, 0x660f60,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklwd",2, 0x0f61, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpcklwd",2, 0x660f61,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpckldq",2, 0x0f62, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"punpckldq",2, 0x660f62,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pxor", 2, 0x0fef, X, CpuMMX, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pxor", 2, 0x660fef,X,CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, /* PIII Katmai New Instructions / SIMD instructions. */ -{"addps", 2, 0x0f58, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addss", 2, 0xf30f58, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"andnps", 2, 0x0f55, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andps", 2, 0x0f54, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpleps", 2, 0x0fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpless", 2, 0xf30fc2, 2, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpltps", 2, 0x0fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpordps", 2, 0x0fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpunordps",2, 0x0fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, FP|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpps", 3, 0x0fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"cmpss", 3, 0xf30fc2, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, -{"comiss", 2, 0x0f2f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, -{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"addps", 2, 0x0f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addss", 2, 0xf30f58, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"andnps", 2, 0x0f55, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andps", 2, 0x0f54, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqps", 2, 0x0fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqss", 2, 0xf30fc2, 0, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpleps", 2, 0x0fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpless", 2, 0xf30fc2, 2, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpltps", 2, 0x0fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltss", 2, 0xf30fc2, 1, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpneqps", 2, 0x0fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqss", 2, 0xf30fc2, 4, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnleps", 2, 0x0fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnless", 2, 0xf30fc2, 6, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpnltps", 2, 0x0fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltss", 2, 0xf30fc2, 5, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpordps", 2, 0x0fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordss", 2, 0xf30fc2, 7, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpunordps",2, 0x0fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordss",2, 0xf30fc2, 3, CpuSSE, NoSuf|IgnoreSize|Modrm|ImmExt, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpps", 3, 0x0fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"cmpss", 3, 0xf30fc2, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|WordMem, RegXMM } }, +{"comiss", 2, 0x0f2f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cvtpi2ps", 2, 0x0f2a, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cvtps2pi", 2, 0x0f2d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, {"cvtsi2ss", 2, 0xf30f2a, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, {"cvtss2si", 2, 0xf30f2d, X, CpuSSE, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvttps2pi", 2, 0x0f2c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, {"cvttss2si", 2, 0xf30f2c, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"divps", 2, 0x0f5e, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divss", 2, 0xf30f5e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, -{"maskmovq", 2, 0x0ff7, X, CpuSSE, FP|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, -{"maxps", 2, 0x0f5f, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxss", 2, 0xf30f5f, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"minps", 2, 0x0f5d, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minss", 2, 0xf30f5d, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f28, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movaps", 2, 0x0f29, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhps", 2, 0x0f17, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlhps", 2, 0x0f16, X, CpuSSE, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f12, X, CpuSSE, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlps", 2, 0x0f13, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"divps", 2, 0x0f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divss", 2, 0xf30f5e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ldmxcsr", 1, 0x0fae, 2, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, +{"maskmovq", 2, 0x0ff7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegMMX, 0 } }, +{"maxps", 2, 0x0f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxss", 2, 0xf30f5f, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"minps", 2, 0x0f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minss", 2, 0xf30f5d, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f28, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movaps", 2, 0x0f29, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhps", 2, 0x0f17, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlhps", 2, 0x0f16, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f12, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlps", 2, 0x0f13, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, {"movmskps", 2, 0x0f50, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntps", 2, 0x0f2b, X, CpuSSE, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movntq", 2, 0x0fe7, X, CpuSSE, FP|Modrm, { RegMMX, LLongMem, 0 } }, -{"movntdq", 2, 0x660fe7, X, CpuSSE2,FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movss", 2, 0xf30f10, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"movss", 2, 0xf30f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, -{"movups", 2, 0x0f10, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movups", 2, 0x0f11, X, CpuSSE, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulps", 2, 0x0f59, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulss", 2, 0xf30f59, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"orps", 2, 0x0f56, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgb", 2, 0x0fe0, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgb", 2, 0x660fe0, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pavgw", 2, 0x0fe3, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pavgw", 2, 0x660fe3, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pextrw", 3, 0x0fc5, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, +{"movntps", 2, 0x0f2b, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntq", 2, 0x0fe7, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX, LLongMem, 0 } }, +{"movntdq", 2, 0x660fe7, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, +{"movss", 2, 0xf30f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"movss", 2, 0xf30f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|WordMem, 0 } }, +{"movups", 2, 0x0f10, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movups", 2, 0x0f11, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulps", 2, 0x0f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulss", 2, 0xf30f59, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"orps", 2, 0x0f56, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgb", 2, 0x0fe0, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgb", 2, 0x660fe0, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pavgw", 2, 0x0fe3, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pavgw", 2, 0x660fe3, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pextrw", 3, 0x0fc5, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegMMX|InvMem, Reg32|Reg64 } }, {"pextrw", 3, 0x660fc5, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, RegXMM|InvMem, Reg32|Reg64 } }, -{"pinsrw", 3, 0x0fc4, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, -{"pinsrw", 3, 0x660fc4, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, -{"pmaxsw", 2, 0x0fee, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxsw", 2, 0x660fee, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmaxub", 2, 0x0fde, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmaxub", 2, 0x660fde, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminsw", 2, 0x0fea, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminsw", 2, 0x660fea, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pminub", 2, 0x0fda, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pminub", 2, 0x660fda, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pmovmskb", 2, 0x0fd7, X, CpuSSE, lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, +{"pinsrw", 3, 0x0fc4, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegMMX } }, +{"pinsrw", 3, 0x660fc4, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { Imm8, Reg32|Reg64|ShortMem, RegXMM } }, +{"pmaxsw", 2, 0x0fee, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxsw", 2, 0x660fee, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmaxub", 2, 0x0fde, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmaxub", 2, 0x660fde, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pminsw", 2, 0x0fea, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminsw", 2, 0x660fea, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pminub", 2, 0x0fda, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pminub", 2, 0x660fda, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmovmskb", 2, 0x0fd7, X, CpuMMX2,lq_Suf|IgnoreSize|Modrm, { RegMMX|InvMem, Reg32|Reg64, 0 } }, {"pmovmskb", 2, 0x660fd7, X, CpuSSE2,lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"pmulhuw", 2, 0x0fe4, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"prefetchnta", 1, 0x0f18, 0, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht0", 1, 0x0f18, 1, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht1", 1, 0x0f18, 2, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"prefetcht2", 1, 0x0f18, 3, CpuSSE, FP|Modrm, { LLongMem, 0, 0 } }, -{"psadbw", 2, 0x0ff6, X, CpuSSE, FP|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, -{"psadbw", 2, 0x660ff6, X, CpuSSE2,FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"pshufw", 3, 0x0f70, X, CpuSSE, FP|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, -{"rcpps", 2, 0x0f53, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rcpss", 2, 0xf30f53, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"rsqrtps", 2, 0x0f52, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"rsqrtss", 2, 0xf30f52, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"sfence", 0, 0x0fae, 0xf8, CpuSSE, FP|ImmExt, { 0, 0, 0 } }, -{"shufps", 3, 0x0fc6, X, CpuSSE, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtps", 2, 0x0f51, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtss", 2, 0xf30f51, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"stmxcsr", 1, 0x0fae, 3, CpuSSE, FP|Modrm, { WordMem, 0, 0 } }, -{"subps", 2, 0x0f5c, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subss", 2, 0xf30f5c, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"ucomiss", 2, 0x0f2e, X, CpuSSE, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"unpckhps", 2, 0x0f15, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklps", 2, 0x0f14, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorps", 2, 0x0f57, X, CpuSSE, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pmulhuw", 2, 0x0fe4, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"pmulhuw", 2, 0x660fe4, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"prefetchnta", 1, 0x0f18, 0, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht0", 1, 0x0f18, 1, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht1", 1, 0x0f18, 2, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, +{"prefetcht2", 1, 0x0f18, 3, CpuMMX2,NoSuf|IgnoreSize|Modrm, { LLongMem, 0, 0 } }, +{"psadbw", 2, 0x0ff6, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegMMX, 0 } }, +{"psadbw", 2, 0x660ff6, X, CpuSSE2,NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"pshufw", 3, 0x0f70, X, CpuMMX2,NoSuf|IgnoreSize|Modrm, { Imm8, RegMMX|LLongMem, RegMMX } }, +{"rcpps", 2, 0x0f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rcpss", 2, 0xf30f53, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"rsqrtps", 2, 0x0f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"rsqrtss", 2, 0xf30f52, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"sfence", 0, 0x0fae, 0xf8, CpuMMX2,NoSuf|IgnoreSize|ImmExt, { 0, 0, 0 } }, +{"shufps", 3, 0x0fc6, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtps", 2, 0x0f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtss", 2, 0xf30f51, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"stmxcsr", 1, 0x0fae, 3, CpuSSE, NoSuf|IgnoreSize|Modrm, { WordMem, 0, 0 } }, +{"subps", 2, 0x0f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subss", 2, 0xf30f5c, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"ucomiss", 2, 0x0f2e, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"unpckhps", 2, 0x0f15, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklps", 2, 0x0f14, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorps", 2, 0x0f57, X, CpuSSE, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, /* SSE-2 instructions. */ -{"addpd", 2, 0x660f58, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsd", 2, 0xf20f58, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"andnpd", 2, 0x660f55, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"andpd", 2, 0x660f54, X, CpuSSE2, FP|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, -{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, -{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, FP|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, -{"cmppd", 3, 0x660fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"addpd", 2, 0x660f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsd", 2, 0xf20f58, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"andnpd", 2, 0x660f55, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"andpd", 2, 0x660f54, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|WordMem, RegXMM, 0 } }, +{"cmpeqpd", 2, 0x660fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpeqsd", 2, 0xf20fc2, 0, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmplepd", 2, 0x660fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmplesd", 2, 0xf20fc2, 2, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpltpd", 2, 0x660fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpltsd", 2, 0xf20fc2, 1, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpneqpd", 2, 0x660fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpneqsd", 2, 0xf20fc2, 4, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpnlepd", 2, 0x660fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnlesd", 2, 0xf20fc2, 6, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpnltpd", 2, 0x660fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpnltsd", 2, 0xf20fc2, 5, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpordpd", 2, 0x660fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpordsd", 2, 0xf20fc2, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmpunordpd",2, 0x660fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpunordsd",2, 0xf20fc2, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm|ImmExt,{ RegXMM|LongMem, RegXMM, 0 } }, +{"cmppd", 3, 0x660fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, /* Intel mode string compare. */ {"cmpsd", 0, 0xa7, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, {"cmpsd", 2, 0xa7, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, -{"comisd", 2, 0x660f2f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, FP|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, +{"cmpsd", 3, 0xf20fc2, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LongMem, RegXMM } }, +{"comisd", 2, 0x660f2f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"cvtpi2pd", 2, 0x660f2a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LLongMem, RegXMM, 0 } }, {"cvtsi2sd", 2, 0xf20f2a, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ Reg32|Reg64|WordMem|LLongMem, RegXMM, 0 } }, -{"divpd", 2, 0x660f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"divsd", 2, 0xf20f5e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"maxpd", 2, 0x660f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maxsd", 2, 0xf20f5f, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"minpd", 2, 0x660f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"minsd", 2, 0xf20f5d, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f28, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movapd", 2, 0x660f29, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movhpd", 2, 0x660f16, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movhpd", 2, 0x660f17, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, -{"movlpd", 2, 0x660f12, X, CpuSSE2, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"movlpd", 2, 0x660f13, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"divpd", 2, 0x660f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"divsd", 2, 0xf20f5e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"maxpd", 2, 0x660f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maxsd", 2, 0xf20f5f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"minpd", 2, 0x660f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"minsd", 2, 0xf20f5d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"movapd", 2, 0x660f28, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movapd", 2, 0x660f29, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movhpd", 2, 0x660f16, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, +{"movhpd", 2, 0x660f17, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, +{"movlpd", 2, 0x660f12, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, +{"movlpd", 2, 0x660f13, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, {"movmskpd", 2, 0x660f50, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm, { RegXMM|InvMem, Reg32|Reg64, 0 } }, -{"movntpd", 2, 0x660f2b, X, CpuSSE2, FP|Modrm, { RegXMM, LLongMem, 0 } }, +{"movntpd", 2, 0x660f2b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, LLongMem, 0 } }, /* Intel mode string move. */ {"movsd", 0, 0xa5, X, 0, NoSuf|Size32|IsString, { 0, 0, 0} }, {"movsd", 2, 0xa5, X, 0, NoSuf|Size32|IsString, { AnyMem, AnyMem|EsSeg, 0} }, -{"movsd", 2, 0xf20f10, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"movsd", 2, 0xf20f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, -{"movupd", 2, 0x660f10, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movupd", 2, 0x660f11, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"mulpd", 2, 0x660f59, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mulsd", 2, 0xf20f59, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"orpd", 2, 0x660f56, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"shufpd", 3, 0x660fc6, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"sqrtpd", 2, 0x660f51, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"subpd", 2, 0x660f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"subsd", 2, 0xf20f5c, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"ucomisd", 2, 0x660f2e, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"unpckhpd", 2, 0x660f15, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"unpcklpd", 2, 0x660f14, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"xorpd", 2, 0x660f57, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, -{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movsd", 2, 0xf20f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"movsd", 2, 0xf20f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LongMem, 0 } }, +{"movupd", 2, 0x660f10, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movupd", 2, 0x660f11, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"mulpd", 2, 0x660f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mulsd", 2, 0xf20f59, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"orpd", 2, 0x660f56, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"shufpd", 3, 0x660fc6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"sqrtpd", 2, 0x660f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"sqrtsd", 2, 0xf20f51, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"subpd", 2, 0x660f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"subsd", 2, 0xf20f5c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"ucomisd", 2, 0x660f2e, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"unpckhpd", 2, 0x660f15, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"unpcklpd", 2, 0x660f14, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"xorpd", 2, 0x660f57, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtdq2pd", 2, 0xf30fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtpd2dq", 2, 0xf20fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtdq2ps", 2, 0x0f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtpd2pi", 2, 0x660f2d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtpd2ps", 2, 0x660f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtps2pd", 2, 0x0f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtps2dq", 2, 0x660f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, {"cvtsd2si", 2, 0xf20f2d, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|LLongMem, Reg32|Reg64, 0 } }, -{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, +{"cvtsd2ss", 2, 0xf20f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvtss2sd", 2, 0xf30f5a, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttpd2pi", 2, 0x660f2c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegMMX, 0 } }, {"cvttsd2si", 2, 0xf20f2c, X, CpuSSE2, lq_Suf|IgnoreSize|Modrm,{ RegXMM|WordMem, Reg32|Reg64, 0 } }, -{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqa", 2, 0x660f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdqu", 2, 0xf30f6f, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movdqu", 2, 0xf30f7f, X, CpuSSE2, FP|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, -{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, FP|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, -{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, FP|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, -{"pmuludq", 2, 0x0ff4, X, CpuSSE2, FP|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmuludq", 2, 0x660ff4, X, CpuSSE2, FP|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, -{"pshufd", 3, 0x660f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshufhw", 3, 0xf30f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pshuflw", 3, 0xf20f70, X, CpuSSE2, FP|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, -{"pslldq", 2, 0x660f73, 7, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, -{"psrldq", 2, 0x660f73, 3, CpuSSE2, FP|Modrm, { Imm8, RegXMM, 0 } }, -{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttpd2dq", 2, 0x660fe6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cvttps2dq", 2, 0xf30f5b, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"maskmovdqu",2, 0x660ff7, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegXMM, 0 } }, +{"movdqa", 2, 0x660f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movdqa", 2, 0x660f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movdqu", 2, 0xf30f6f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movdqu", 2, 0xf30f7f, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM, RegXMM|LLongMem, 0 } }, +{"movdq2q", 2, 0xf20fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|InvMem, RegMMX, 0 } }, +{"movq2dq", 2, 0xf30fd6, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|InvMem, RegXMM, 0 } }, +{"pmuludq", 2, 0x0ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmuludq", 2, 0x660ff4, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LongMem, RegXMM, 0 } }, +{"pshufd", 3, 0x660f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pshufhw", 3, 0xf30f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pshuflw", 3, 0xf20f70, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM|LLongMem, RegXMM } }, +{"pslldq", 2, 0x660f73, 7, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"psrldq", 2, 0x660f73, 3, CpuSSE2, NoSuf|IgnoreSize|Modrm, { Imm8, RegXMM, 0 } }, +{"punpckhqdq",2, 0x660f6d, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"punpcklqdq",2, 0x660f6c, X, CpuSSE2, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, /* Prescott New Instructions. */ -{"addsubpd", 2, 0x660fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"addsubps", 2, 0xf20fd0, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|FloatMF|Modrm, { ShortMem|LongMem, 0, 0} }, -/* Intel Syntax */ -{"fisttpd", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"fisttpq", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, +{"addsubpd", 2, 0x660fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"addsubps", 2, 0xf20fd0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"cmpxchg16b",1, 0x0fc7, 1, CpuPNI|Cpu64, NoSuf|Modrm|Rex64, { LLongMem, 0, 0} }, +{"fisttp", 1, 0xdf, 1, CpuPNI, sl_FP|Modrm, { ShortMem|LongMem, 0, 0} }, +{"fisttp", 1, 0xdd, 1, CpuPNI, q_FP|Modrm, { LLongMem, 0, 0} }, {"fisttpll", 1, 0xdd, 1, CpuPNI, FP|Modrm, { LLongMem, 0, 0} }, -{"haddpd", 2, 0x660f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"haddps", 2, 0xf20f7c, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubpd", 2, 0x660f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"hsubps", 2, 0xf20f7d, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"lddqu", 2, 0xf20ff0, X, CpuPNI, FP|Modrm, { LLongMem, RegXMM, 0 } }, -{"monitor", 0, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +{"haddpd", 2, 0x660f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"haddps", 2, 0xf20f7c, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubpd", 2, 0x660f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"hsubps", 2, 0xf20f7d, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"lddqu", 2, 0xf20ff0, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { LLongMem, RegXMM, 0 } }, +{"monitor", 0, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, /* Need to ensure only "monitor %eax,%ecx,%edx" is accepted. */ -{"monitor", 3, 0x0f01, 0xc8, CpuPNI, FP|ImmExt, { Reg32, Reg32, Reg32} }, -{"movddup", 2, 0xf20f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movshdup", 2, 0xf30f16, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"movsldup", 2, 0xf30f12, X, CpuPNI, FP|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, -{"mwait", 0, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { 0, 0, 0} }, +{"monitor", 3, 0x0f01, 0xc8, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, Reg32} }, +{"movddup", 2, 0xf20f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movshdup", 2, 0xf30f16, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"movsldup", 2, 0xf30f12, X, CpuPNI, NoSuf|IgnoreSize|Modrm, { RegXMM|LLongMem, RegXMM, 0 } }, +{"mwait", 0, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { 0, 0, 0} }, /* Need to ensure only "mwait %eax,%ecx" is accepted. */ -{"mwait", 2, 0x0f01, 0xc9, CpuPNI, FP|ImmExt, { Reg32, Reg32, 0} }, +{"mwait", 2, 0x0f01, 0xc9, CpuPNI, NoSuf|ImmExt, { Reg32, Reg32, 0} }, /* AMD 3DNow! instructions. */ -{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, -{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, FP|Modrm, { ByteMem, 0, 0 } }, -{"femms", 0, 0x0f0e, X, Cpu3dnow, FP, { 0, 0, 0 } }, -{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, -{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnow|Cpu686, FP|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"prefetch", 1, 0x0f0d, 0, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, +{"prefetchw",1, 0x0f0d, 1, Cpu3dnow, NoSuf|IgnoreSize|Modrm, { ByteMem, 0, 0 } }, +{"femms", 0, 0x0f0e, X, Cpu3dnow, NoSuf, { 0, 0, 0 } }, +{"pavgusb", 2, 0x0f0f, 0xbf, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2id", 2, 0x0f0f, 0x1d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pf2iw", 2, 0x0f0f, 0x1c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfacc", 2, 0x0f0f, 0xae, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfadd", 2, 0x0f0f, 0x9e, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpeq", 2, 0x0f0f, 0xb0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpge", 2, 0x0f0f, 0x90, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfcmpgt", 2, 0x0f0f, 0xa0, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmax", 2, 0x0f0f, 0xa4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmin", 2, 0x0f0f, 0x94, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfmul", 2, 0x0f0f, 0xb4, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfnacc", 2, 0x0f0f, 0x8a, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfpnacc", 2, 0x0f0f, 0x8e, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcp", 2, 0x0f0f, 0x96, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit1", 2, 0x0f0f, 0xa6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrcpit2", 2, 0x0f0f, 0xb6, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqit1", 2, 0x0f0f, 0xa7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfrsqrt", 2, 0x0f0f, 0x97, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsub", 2, 0x0f0f, 0x9a, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pfsubr", 2, 0x0f0f, 0xaa, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fd", 2, 0x0f0f, 0x0d, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pi2fw", 2, 0x0f0f, 0x0c, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pmulhrw", 2, 0x0f0f, 0xb7, Cpu3dnow, NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, +{"pswapd", 2, 0x0f0f, 0xbb, Cpu3dnowA,NoSuf|IgnoreSize|Modrm|ImmExt, { RegMMX|LongMem, RegMMX, 0 } }, /* AMD extensions. */ {"syscall", 0, 0x0f05, X, CpuK6, NoSuf, { 0, 0, 0} }, {"sysret", 0, 0x0f07, X, CpuK6, lq_Suf|DefaultSize, { 0, 0, 0} }, {"swapgs", 0, 0x0f01, 0xf8, Cpu64, NoSuf|ImmExt, { 0, 0, 0} }, +{"rdtscp", 0, 0x0f01, 0xf9, CpuSledgehammer,NoSuf|ImmExt, { 0, 0, 0} }, -/* VIA PadLock extensions. */ -{"xstorerng", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +/* VIA PadLock extensions. */ +{"xstorerng", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, {"xcryptecb", 0, 0xf30fa7c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, {"xcryptcbc", 0, 0xf30fa7d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, {"xcryptcfb", 0, 0xf30fa7e0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, {"xcryptofb", 0, 0xf30fa7e8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, -/* alias for xstorerng */ -{"xstore", 0, 0x0fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"montmul", 0, 0xf30fa6c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xsha1", 0, 0xf30fa6c8, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +{"xsha256", 0, 0xf30fa6d0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, +/* Alias for xstorerng. */ +{"xstore", 0, 0x000fa7c0, X, Cpu686|CpuPadLock, NoSuf|IsString, { 0, 0, 0} }, /* sentinel */ {NULL, 0, 0, 0, 0, 0, { 0, 0, 0} } @@ -1389,16 +1402,17 @@ static const template i386_optab[] = { #undef bwlq_Suf #undef FP #undef l_FP +#undef q_FP #undef x_FP #undef sl_FP -#define MAX_MNEM_SIZE 16 /* for parsing insn mnemonics from input */ - +#define MAX_MNEM_SIZE 16 /* For parsing insn mnemonics from input. */ /* 386 register table. */ -static const reg_entry i386_regtab[] = { - /* make %st first as we test for it */ +static const reg_entry i386_regtab[] = +{ + /* Make %st first as we test for it. */ {"st", FloatReg|FloatAcc, 0, 0}, /* 8 bit regs */ #define REGNAM_AL 1 /* Entry in i386_regtab. */ @@ -1446,7 +1460,7 @@ static const reg_entry i386_regtab[] = { {"r15w", Reg16, RegRex, 7}, /* 32 bit regs */ #define REGNAM_EAX 41 - {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot */ + {"eax", Reg32|BaseIndex|Acc, 0, 0}, /* Must be in ax + 16 slot. */ {"ecx", Reg32|BaseIndex, 0, 1}, {"edx", Reg32|BaseIndex, 0, 2}, {"ebx", Reg32|BaseIndex, 0, 3}, @@ -1478,14 +1492,14 @@ static const reg_entry i386_regtab[] = { {"r13", Reg64|BaseIndex, RegRex, 5}, {"r14", Reg64|BaseIndex, RegRex, 6}, {"r15", Reg64|BaseIndex, RegRex, 7}, - /* segment registers */ + /* Segment registers. */ {"es", SReg2, 0, 0}, {"cs", SReg2, 0, 1}, {"ss", SReg2, 0, 2}, {"ds", SReg2, 0, 3}, {"fs", SReg3, 0, 4}, {"gs", SReg3, 0, 5}, - /* control registers */ + /* Control registers. */ {"cr0", Control, 0, 0}, {"cr1", Control, 0, 1}, {"cr2", Control, 0, 2}, @@ -1502,7 +1516,7 @@ static const reg_entry i386_regtab[] = { {"cr13", Control, RegRex, 5}, {"cr14", Control, RegRex, 6}, {"cr15", Control, RegRex, 7}, - /* debug registers */ + /* Debug registers. */ {"db0", Debug, 0, 0}, {"db1", Debug, 0, 1}, {"db2", Debug, 0, 2}, @@ -1535,7 +1549,7 @@ static const reg_entry i386_regtab[] = { {"dr13", Debug, RegRex, 5}, {"dr14", Debug, RegRex, 6}, {"dr15", Debug, RegRex, 7}, - /* test registers */ + /* Test registers. */ {"tr0", Test, 0, 0}, {"tr1", Test, 0, 1}, {"tr2", Test, 0, 2}, @@ -1544,7 +1558,7 @@ static const reg_entry i386_regtab[] = { {"tr5", Test, 0, 5}, {"tr6", Test, 0, 6}, {"tr7", Test, 0, 7}, - /* mmx and simd registers */ + /* MMX and simd registers. */ {"mm0", RegMMX, 0, 0}, {"mm1", RegMMX, 0, 1}, {"mm2", RegMMX, 0, 2}, @@ -1569,12 +1583,13 @@ static const reg_entry i386_regtab[] = { {"xmm13", RegXMM, RegRex, 5}, {"xmm14", RegXMM, RegRex, 6}, {"xmm15", RegXMM, RegRex, 7}, - /* no type will make this register rejected for all purposes except + /* No type will make this register rejected for all purposes except for addressing. This saves creating one extra type for RIP. */ {"rip", BaseIndex, 0, 0} }; -static const reg_entry i386_float_regtab[] = { +static const reg_entry i386_float_regtab[] = +{ {"st(0)", FloatReg|FloatAcc, 0, 0}, {"st(1)", FloatReg, 0, 1}, {"st(2)", FloatReg, 0, 2}, @@ -1585,9 +1600,9 @@ static const reg_entry i386_float_regtab[] = { {"st(7)", FloatReg, 0, 7} }; -#define MAX_REG_NAME_SIZE 8 /* for parsing register names from input */ +#define MAX_REG_NAME_SIZE 8 /* For parsing register names from input. */ -/* segment stuff */ +/* Segment stuff. */ static const seg_entry cs = { "cs", 0x2e }; static const seg_entry ds = { "ds", 0x3e }; static const seg_entry ss = { "ss", 0x36 }; @@ -1595,4 +1610,3 @@ static const seg_entry es = { "es", 0x26 }; static const seg_entry fs = { "fs", 0x64 }; static const seg_entry gs = { "gs", 0x65 }; -/* end of opcode/i386.h */ diff --git a/gnu/dist/binutils/include/opcode/i860.h b/gnu/dist/binutils/include/opcode/i860.h index b46a5e5a4eb..fe08ee4f228 100644 --- a/gnu/dist/binutils/include/opcode/i860.h +++ b/gnu/dist/binutils/include/opcode/i860.h @@ -1,5 +1,5 @@ /* Table of opcodes for the i860. - Copyright 1989, 1991, 2000, 2003 Free Software Foundation, Inc. + Copyright 1989, 1991, 2000, 2002, 2003 Free Software Foundation, Inc. This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. diff --git a/gnu/dist/binutils/include/opcode/ia64.h b/gnu/dist/binutils/include/opcode/ia64.h index 0d33fc61b2c..58553b3ad63 100644 --- a/gnu/dist/binutils/include/opcode/ia64.h +++ b/gnu/dist/binutils/include/opcode/ia64.h @@ -1,5 +1,5 @@ /* ia64.h -- Header file for ia64 opcode table - Copyright (C) 1998, 1999, 2002 Free Software Foundation, Inc. + Copyright (C) 1998, 1999, 2000, 2002 Free Software Foundation, Inc. Contributed by David Mosberger-Tang <davidm@hpl.hp.com> */ #ifndef opcode_ia64_h diff --git a/gnu/dist/binutils/include/opcode/m68k.h b/gnu/dist/binutils/include/opcode/m68k.h index 3f189841d8f..014495b9720 100644 --- a/gnu/dist/binutils/include/opcode/m68k.h +++ b/gnu/dist/binutils/include/opcode/m68k.h @@ -1,6 +1,6 @@ /* Opcode table header for m680[01234]0/m6888[12]/m68851. Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1999, 2001, - 2003 Free Software Foundation, Inc. + 2003, 2004 Free Software Foundation, Inc. This file is part of GDB, GAS, and the GNU binutils. @@ -35,13 +35,27 @@ #define m68881 0x040 #define m68882 m68881 /* Synonym for -m68881. otherwise unused. */ #define m68851 0x080 -#define cpu32 0x100 /* e.g., 68332 */ -#define mcf5200 0x200 -#define mcf5206e 0x400 -#define mcf5307 0x800 -#define mcf5407 0x1000 -#define mcfv4e 0x2000 -#define mcf528x 0x4000 +#define cpu32 0x100 /* e.g., 68332 */ + +#define mcfmac 0x200 /* ColdFire MAC. */ +#define mcfemac 0x400 /* ColdFire EMAC. */ +#define cfloat 0x800 /* ColdFire FPU. */ +#define mcfhwdiv 0x1000 /* ColdFire hardware divide. */ + +#define mcfisa_a 0x2000 /* ColdFire ISA_A. */ +#define mcfisa_aa 0x4000 /* ColdFire ISA_A+. */ +#define mcfisa_b 0x8000 /* ColdFire ISA_B. */ +#define mcfusp 0x10000 /* ColdFire USP instructions. */ + +#define mcf5200 0x20000 +#define mcf5206e 0x40000 +#define mcf521x 0x80000 +#define mcf5249 0x100000 +#define mcf528x 0x200000 +#define mcf5307 0x400000 +#define mcf5407 0x800000 +#define mcf5470 0x1000000 +#define mcf5480 0x2000000 /* Handy aliases. */ #define m68040up (m68040 | m68060) @@ -49,13 +63,7 @@ #define m68020up (m68020 | m68030up) #define m68010up (m68010 | cpu32 | m68020up) #define m68000up (m68000 | m68010up) -#define mcf (mcf5200 | mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) -#define mcf5206eup (mcf5206e | mcf528x | mcf5307 | mcf5407 | mcfv4e) -#define mcf5307up (mcf5307 | mcf5407 | mcfv4e) -#define mcfv4up (mcf5407 | mcfv4e) -#define mcfv4eup (mcfv4e) -#define cfloat (mcfv4e) #define mfloat (m68881 | m68882 | m68040 | m68060) #define mmmu (m68851 | m68030 | m68040 | m68060) @@ -65,6 +73,9 @@ struct m68k_opcode { /* The opcode name. */ const char *name; + /* The pseudo-size of the instruction(in bytes). Used to determine + number of bytes necessary to disassemble the instruction. */ + unsigned int size; /* The opcode itself. */ unsigned long opcode; /* The mask used by the disassembler. */ @@ -99,7 +110,7 @@ struct m68k_opcode_alias operand; the second, the place it is stored. */ /* Kinds of operands: - Characters used: AaBbCcDdEFfGHIJkLlMmnOopQqRrSsTtU VvWwXxYyZz0123|*~%;@!&$?/<>#^+- + Characters used: AaBbCcDdEeFfGgHIiJkLlMmnOopQqRrSsTtU VvWwXxYyZz01234|*~%;@!&$?/<>#^+- D data register only. Stored as 3 bits. A address register only. Stored as 3 bits. @@ -133,9 +144,12 @@ struct m68k_opcode_alias C the CCR. No need to store it; this is just for filtering validity. S the SR. No need to store, just as with CCR. U the USP. No need to store, just as with CCR. - E the ACC. No need to store, just as with CCR. - G the MACSR. No need to store, just as with CCR. + E the MAC ACC. No need to store, just as with CCR. + e the EMAC ACC[0123]. + G the MAC/EMAC MACSR. No need to store, just as with CCR. + g the EMAC ACCEXT{01,23}. H the MASK. No need to store, just as with CCR. + i the MAC/EMAC scale factor. I Coprocessor ID. Not printed if 1. The Coprocessor ID is always extracted from the 'd' field of word one, which means that an extended @@ -205,7 +219,7 @@ struct m68k_opcode_alias ! control (modes 2,5,6,7.0-3) (not 0,1,3,4,7.4) & alterable control (modes 2,5,6,7.0,7.1) - (not 0,1,7.2-4) + (not 0,1,3,4,7.2-4) $ alterable data (modes 0,2-6,7.0,7.1) (not 1,7.2-4) ? alterable control, or data register (modes 0,2,5,6,7.0,7.1) @@ -230,7 +244,9 @@ struct m68k_opcode_alias w (modes 2-5,7.2) y (modes 2,5) z (modes 2,5,7.2) - x mov3q immediate operand. */ + x mov3q immediate operand. + 4 (modes 2,3,4,5) + */ /* For the 68851: */ /* I didn't use much imagination in choosing the @@ -283,7 +299,7 @@ struct m68k_opcode_alias */ /* Places to put an operand, for non-general operands: - Characters used: BbCcDdghijkLlMmNnostWw123456789 + Characters used: BbCcDdFfGgHhIijkLlMmNnostWw123456789/ s source, low bits of first word. d dest, shifted 9 in first word @@ -348,6 +364,13 @@ struct m68k_opcode_alias F double precision float, low bit of 1st word, immediate uses 8 bytes x extended precision float, low bit of 1st word, immediate uses 12 bytes p packed float, low bit of 1st word, immediate uses 12 bytes + G EMAC accumulator, load (bit 4 2nd word, !bit8 first word) + H EMAC accumulator, non load (bit 4 2nd word, bit 8 first word) + F EMAC ACCx + f EMAC ACCy + I MAC/EMAC scale factor + / Like 's', but set 2nd word, bit 5 if trailing_ampersand set + ] first word, bit 10 */ extern const struct m68k_opcode m68k_opcodes[]; diff --git a/gnu/dist/binutils/include/opcode/m88k.h b/gnu/dist/binutils/include/opcode/m88k.h index 6a163bbe934..c201349dc52 100644 --- a/gnu/dist/binutils/include/opcode/m88k.h +++ b/gnu/dist/binutils/include/opcode/m88k.h @@ -1,5 +1,6 @@ /* Table of opcodes for the Motorola M88k family. - Copyright 1989, 1990, 1991, 1993, 2001 Free Software Foundation, Inc. + Copyright 1989, 1990, 1991, 1993, 2001, 2002 + Free Software Foundation, Inc. This file is part of GDB and GAS. diff --git a/gnu/dist/binutils/include/opcode/maxq.h b/gnu/dist/binutils/include/opcode/maxq.h new file mode 100644 index 00000000000..f4fcb30a80c --- /dev/null +++ b/gnu/dist/binutils/include/opcode/maxq.h @@ -0,0 +1,1132 @@ +/* maxq.h -- Header file for MAXQ opcode table. + + Copyright (C) 2004 Free Software Foundation, Inc. + + This file is part of GDB, GAS, and the GNU binutils. + + Written by Vineet Sharma(vineets@noida.hcltech.com) + Inderpreet Singh (inderpreetb@noida.hcltech.com) + + GDB, GAS, and the GNU binutils are free software; you can redistribute + them and/or modify them under the terms of the GNU General Public License + as published by the Free Software Foundation; either version 2, or (at + your option) any later version. + + GDB, GAS, and the GNU binutils are distributed in the hope that they will + be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General + Public License for more details. + + You should have received a copy of the GNU General Public License along + with this file; see the file COPYING. If not, write to the Free Software + Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ + +#ifndef _MAXQ20_H_ +#define _MAXQ20_H_ + +/* This file contains the opcode table for the MAXQ10/20 processor. The table + has been designed on the lines of the SH processor with the following + fields: + (1) Instruction Name + (2) Instruction arguments description + (3) Description of the breakup of the opcode (1+7+8|8+8|1+4+4|1+7+1+3+4 + |1+3+4+1+3+4|1+3+4+8|1+1+2+4+8) + (4) Architecture supported + + The Register table is also defined. It contains the following fields + (1) Register name + (2) Module Number + (3) Module Index + (4) Opcode + (5) Regtype + + The Memory access table is defined containing the various opcodes for + memory access containing the following fields + (1) Memory access Operand Name + (2) Memory access Operand opcode. */ + +# define MAXQ10 0x0001 +# define MAXQ20 0x0002 +# define MAX (MAXQ10 | MAXQ20) + +/* This is for the NOP instruction Specify : 1st bit : NOP_FMT 1st byte: + NOP_DST 2nd byte: NOP_SRC. */ +# define NOP_FMT 1 +# define NOP_SRC 0x3A +# define NOP_DST 0x5A + +typedef enum +{ + ZEROBIT = 0x1, /* A zero followed by 3 bits. */ + ONEBIT = 0x2, /* A one followed by 3 bits. */ + REG = 0x4, /* Register. */ + MEM = 0x8, /* Memory access. */ + IMM = 0x10, /* Immediate value. */ + DISP = 0x20, /* Displacement value. */ + BIT = 0x40, /* Bit value. */ + FMT = 0x80, /* The format bit. */ + IMMBIT = 0x100, /* An immediate bit. */ + FLAG = 0x200, /* A Flag. */ + DATA = 0x400, /* Symbol in the data section. */ + BIT_BUCKET = 0x800, /* FOr BIT BUCKET. */ +} +UNKNOWN_OP; + +typedef enum +{ + NO_ARG = 0, + A_IMM = 0x01, /* An 8 bit immediate value. */ + A_REG = 0x2, /* An 8 bit source register. */ + A_MEM = 0x4, /* A 7 bit destination register. */ + FLAG_C = 0x8, /* Carry Flag. */ + FLAG_NC = 0x10, /* No Carry (~C) flag. */ + FLAG_Z = 0x20, /* Zero Flag. */ + FLAG_NZ = 0x40, /* Not Zero Flag. */ + FLAG_S = 0x80, /* Sign Flag. */ + FLAG_E = 0x100, /* Equals Flag. */ + FLAG_NE = 0x200, /* Not Equal Flag. */ + ACC_BIT = 0x400, /* One of the 16 accumulator bits of the form Acc.<b>. */ + DST_BIT = 0x800, /* One of the 8 bits of the specified SRC. */ + SRC_BIT = 0x1000, /* One of the 8 bits of the specified source register. */ + A_BIT_0 = 0x2000, /* #0. */ + A_BIT_1 = 0x4000, /* #1. */ + A_DISP = 0x8000, /* Displacement Operand. */ + A_DATA = 0x10000, /* Data in the data section. */ + A_BIT_BUCKET = 0x200000, +} +MAX_ARG_TYPE; + +typedef struct +{ + char * name; /* Name of the instruction. */ + unsigned int op_number; /* Operand Number or the number of operands. */ + MAX_ARG_TYPE arg[2]; /* Types of operands. */ + int format; /* Format bit. */ + int dst[2]; /* Destination in the move instruction. */ + int src[2]; /* Source in the move instruction. */ + int arch; /* The Machine architecture. */ + unsigned int instr_id; /* Added for decode and dissassembly. */ +} +MAXQ20_OPCODE_INFO; + +/* Structure for holding opcodes of the same name. */ +typedef struct +{ + const MAXQ20_OPCODE_INFO *start; /* The first opcode. */ + const MAXQ20_OPCODE_INFO *end; /* The last opcode. */ +} +MAXQ20_OPCODES; + +/* The entry into the hash table will be of the type MAXX_OPCODES. */ + +/* The definition of the table. */ +const MAXQ20_OPCODE_INFO op_table[] = +{ + /* LOGICAL OPERATIONS */ + /* AND src : f001 1010 ssss ssss */ + {"AND", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x1a, 0}, + {REG | MEM | IMM | DISP, 0}, MAX, 0x11}, + /* AND Acc.<b> : 1111 1010 bbbb 1010 */ + {"AND", 1, {ACC_BIT, 0}, 1, {0x1a, 0}, {BIT, 0xa}, MAX, 0x39}, + /* OR src : f010 1010 ssss ssss */ + {"OR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x2a, 0}, + {REG | MEM | IMM | DISP, 0}, MAX, 0x12}, + /* OR Acc.<b> : 1010 1010 bbbb 1010 */ + {"OR", 1, {ACC_BIT, 0}, 1, {0x2a, 0}, {BIT, 0xa}, MAX, 0x3A}, + /* XOR src : f011 1010 ssss ssss */ + {"XOR", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3a, 0}, + {REG | MEM | IMM | DISP, 0}, MAX, 0x13}, + /* XOR Acc.<b> : 1011 1010 bbbb 1010 */ + {"XOR", 1, {ACC_BIT, 0}, 1, {0x3a, 0}, {BIT, 0xa}, MAX, 0x3B}, + /* LOGICAL OPERATIONS INVOLVING ONLY THE ACCUMULATOR */ + /* CPL : 1000 1010 0001 1010 */ + {"CPL", 0, {0, 0}, 1, {0x0a, 0}, {0x1a, 0}, MAX, 0x21}, + /* CPL C : 1101 1010 0010 1010 */ + {"CPL", 1, {FLAG_C, 0}, 1, {0x5a, 0}, {0x2a, 0}, MAX, 0x3D}, + /* NEG : 1000 1010 1001 1010 */ + {"NEG", 0, {0, 0}, 1, {0x0a, 0}, {0x9a, 0}, MAX, 0x29}, + /* SLA : 1000 1010 0010 1010 */ + {"SLA", 0, {0, 0}, 1, {0x0a, 0}, {0x2a, 0}, MAX, 0x22}, + /* SLA2: 1000 1010 0011 1010 */ + {"SLA2", 0, {0, 0}, 1, {0x0a, 0}, {0x3a, 0}, MAX, 0x23}, + /* SLA4: 1000 1010 0110 1010 */ + {"SLA4", 0, {0, 0}, 1, {0x0a, 0}, {0x6a, 0}, MAX, 0x26}, + /* RL : 1000 1010 0100 1010 */ + {"RL", 0, {0, 0}, 1, {0x0a, 0}, {0x4a, 0}, MAX, 0x24}, + /* RLC : 1000 1010 0101 1010 */ + {"RLC", 0, {0, 0}, 1, {0x0a, 0}, {0x5a, 0}, MAX, 0x25}, + /* SRA : 1000 1010 1111 1010 */ + {"SRA", 0, {0, 0}, 1, {0x0a, 0}, {0xfa, 0}, MAX, 0x2F}, + /* SRA2: 1000 1010 1110 1010 */ + {"SRA2", 0, {0, 0}, 1, {0x0a, 0}, {0xea, 0}, MAX, 0x2E}, + /* SRA4: 1000 1010 1011 1010 */ + {"SRA4", 0, {0, 0}, 1, {0x0a, 0}, {0xba, 0}, MAX, 0x2B}, + /* SR : 1000 1010 1010 1010 */ + {"SR", 0, {0, 0}, 1, {0x0a, 0}, {0xaa, 0}, MAX, 0x2A}, + /* RR : 1000 1010 1100 1010 */ + {"RR", 0, {0, 0}, 1, {0x0a, 0}, {0xca, 0}, MAX, 0x2C}, + /* RRC : 1000 1010 1101 1010 */ + {"RRC", 0, {0, 0}, 1, {0x0a, 0}, {0xda, 0}, MAX, 0x2D}, + /* MATH OPERATIONS */ + /* ADD src : f100 1010 ssss ssss */ + {"ADD", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x4a, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x14}, + /* ADDC src : f110 1010 ssss ssss */ + {"ADDC", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x6a, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x16}, + /* SUB src : f101 1010 ssss ssss */ + {"SUB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x5a, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x15}, + /* SUBB src : f111 1010 ssss ssss */ + {"SUBB", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x7a, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x17}, + /* BRANCHING OPERATIONS */ + + /* DJNZ LC[0] src: f100 1101 ssss ssss */ + {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4d, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0xA4}, + /* DJNZ LC[1] src: f101 1101 ssss ssss */ + {"DJNZ", 2, {A_REG, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5d, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0xA5}, + /* CALL src : f011 1101 ssss ssss */ + {"CALL", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x3d, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0xA3}, + /* JUMP src : f000 1100 ssss ssss */ + {"JUMP", 1, {A_IMM | A_REG | A_MEM | A_DISP, 0}, FMT, {0x0c, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x50}, + /* JUMP C,src : f010 1100 ssss ssss */ + {"JUMP", 2, {FLAG_C, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x2c, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x52}, + /* JUMP NC,src: f110 1100 ssss ssss */ + {"JUMP", 2, {FLAG_NC, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x6c, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x56}, + /* JUMP Z,src : f001 1100 ssss ssss */ + {"JUMP", 2, {FLAG_Z, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x1c, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x51}, + /* JUMP NZ,src: f101 1100 ssss ssss */ + {"JUMP", 2, {FLAG_NZ, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x5c, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x55}, + /* JUMP E,src : 0011 1100 ssss ssss */ + {"JUMP", 2, {FLAG_E, A_IMM | A_DISP}, 0, {0x3c, 0}, {IMM, 0}, MAX, 0x53}, + /* JUMP NE,src: 0111 1100 ssss ssss */ + {"JUMP", 2, {FLAG_NE, A_IMM | A_DISP}, 0, {0x7c, 0}, {IMM, 0}, MAX, 0x57}, + /* JUMP S,src : f100 1100 ssss ssss */ + {"JUMP", 2, {FLAG_S, A_IMM | A_REG | A_MEM | A_DISP}, FMT, {0x4c, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0x54}, + /* RET : 1000 1100 0000 1101 */ + {"RET", 0, {0, 0}, 1, {0x0c, 0}, {0x0d, 0}, MAX, 0x68}, + /* RET C : 1010 1100 0000 1101 */ + {"RET", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x0d, 0}, MAX, 0x6A}, + /* RET NC : 1110 1100 0000 1101 */ + {"RET", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x0d, 0}, MAX, 0x6E}, + /* RET Z : 1001 1100 0000 1101 */ + {"RET", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x0d, 0}, MAX, 0x69}, + /* RET NZ : 1101 1100 0000 1101 */ + {"RET", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x0d, 0}, MAX, 0x6D}, + /* RET S : 1100 1100 0000 1101 */ + {"RET", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x0d, 0}, MAX, 0x6C}, + /* RETI : 1000 1100 1000 1101 */ + {"RETI", 0, {0, 0}, 1, {0x0c, 0}, {0x8d, 0}, MAX, 0x78}, + /* ADDED ACCORDING TO NEW SPECIFICATION */ + + /* RETI C : 1010 1100 1000 1101 */ + {"RETI", 1, {FLAG_C, 0}, 1, {0x2c, 0}, {0x8d, 0}, MAX, 0x7A}, + /* RETI NC : 1110 1100 1000 1101 */ + {"RETI", 1, {FLAG_NC, 0}, 1, {0x6c, 0}, {0x8d, 0}, MAX, 0x7E}, + /* RETI Z : 1001 1100 1000 1101 */ + {"RETI", 1, {FLAG_Z, 0}, 1, {0x1c, 0}, {0x8d, 0}, MAX, 0x79}, + /* RETI NZ : 1101 1100 1000 1101 */ + {"RETI", 1, {FLAG_NZ, 0}, 1, {0x5c, 0}, {0x8d, 0}, MAX, 0x7D}, + /* RETI S : 1100 1100 1000 1101 */ + {"RETI", 1, {FLAG_S, 0}, 1, {0x4c, 0}, {0x8d, 0}, MAX, 0x7C}, + /* MISCELLANEOUS INSTRUCTIONS */ + /* CMP src : f111 1000 ssss ssss */ + {"CMP", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x78, 0}, + {REG | MEM | IMM | DISP, 0}, MAX, 0xD7}, + /* DATA TRANSFER OPERATIONS */ + /* XCH : 1000 1010 1000 1010 */ + {"XCH", 0, {0, 0}, 1, {0x0a, 0}, {0x8a, 0}, MAXQ20, 0x28}, + /* XCHN : 1000 1010 0111 1010 */ + {"XCHN", 0, {0, 0}, 1, {0x0a, 0}, {0x7a, 0}, MAX, 0x27}, + /* PUSH src : f000 1101 ssss ssss */ + {"PUSH", 1, {A_REG | A_IMM | A_MEM | A_DISP, 0}, FMT, {0x0d, 0}, + {IMM | REG | MEM | DISP, 0}, MAX, 0xA0}, + /* POP dst : 1ddd dddd 0000 1101 */ + {"POP", 1, {A_REG, 0}, 1, {REG, 0}, {0x0d, 0}, MAX, 0xB0}, + /* Added according to new spec */ + /* POPI dst : 1ddd dddd 1000 1101 */ + {"POPI", 1, {A_REG, 0}, 1, {REG, 0}, {0x8d, 0}, MAX, 0xC0}, + /* MOVE dst,src: fddd dddd ssss ssss */ + {"MOVE", 2, {A_REG | A_MEM, A_REG | A_IMM | A_MEM | A_DATA | A_DISP}, FMT, + {REG | MEM, 0}, {REG | IMM | MEM | DATA | A_DISP, 0}, MAX, 0x80}, + /* BIT OPERATIONS */ + /* MOVE C,Acc.<b> : 1110 1010 bbbb 1010 */ + {"MOVE", 2, {FLAG_C, ACC_BIT}, 1, {0x6a, 0}, {BIT, 0xa}, MAX, 0x3E}, + /* MOVE C,#0 : 1101 1010 0000 1010 */ + {"MOVE", 2, {FLAG_C, A_BIT_0}, 1, {0x5a, 0}, {0x0a, 0}, MAX, 0x3D}, + /* MOVE C,#1 : 1101 1010 0001 1010 */ + {"MOVE", 2, {FLAG_C, A_BIT_1}, 1, {0x5a, 0}, {0x1a, 0}, MAX, 0x3D}, + /* MOVE Acc.<b>,C : 1111 1010 bbbb 1010 */ + {"MOVE", 2, {ACC_BIT, FLAG_C}, 1, {0x7a, 0}, {BIT, 0xa}, MAX, 0x3F}, + /* MOVE dst.<b>,#0 : 1ddd dddd 0bbb 0111 */ + {"MOVE", 2, {DST_BIT, A_BIT_0}, 1, {REG, 0}, {ZEROBIT, 0x7}, MAX, 0x40}, + /* MOVE dst.<b>,#1 : 1ddd dddd 1bbb 0111 */ + {"MOVE", 2, {DST_BIT, A_BIT_1}, 1, {REG, 0}, {ONEBIT, 0x7}, MAX, 0x41}, + /* MOVE C,src.<b> : fbbb 0111 ssss ssss */ + {"MOVE", 2, {FLAG_C, SRC_BIT}, FMT, {BIT, 0x7}, {REG, 0}, MAX, 0x97}, + /* NOP : 1101 1010 0011 1010 */ + {"NOP", 0, {0, 0}, NOP_FMT, {NOP_DST, 0}, {NOP_SRC, 0}, MAX, 0x3D}, + {NULL, 0, {0, 0}, 0, {0, 0}, {0, 0}, 0, 0x00} +}; + +/* All the modules. */ + +#define MOD0 0x0 +#define MOD1 0x1 +#define MOD2 0x2 +#define MOD3 0x3 +#define MOD4 0x4 +#define MOD5 0x5 +#define MOD6 0x6 +#define MOD7 0x7 +#define MOD8 0x8 +#define MOD9 0x9 +#define MODA 0xa +#define MODB 0xb +#define MODC 0xc +#define MODD 0xd +#define MODE 0xe +#define MODF 0xf + +/* Added according to new specification. */ +#define MOD10 0x10 +#define MOD11 0x11 +#define MOD12 0x12 +#define MOD13 0x13 +#define MOD14 0x14 +#define MOD15 0x15 +#define MOD16 0x16 +#define MOD17 0x17 +#define MOD18 0x18 +#define MOD19 0x19 +#define MOD1A 0x1a +#define MOD1B 0x1b +#define MOD1C 0x1c +#define MOD1D 0x1d +#define MOD1E 0x1e +#define MOD1F 0x1f + +/* - Peripheral Register Modules - */ +/* Serial Register Modules. */ +#define CTRL MOD8 /* For the module containing the control registers. */ +#define ACC MOD9 /* For the module containing the 16 accumulators. */ +#define Act_ACC MODA /* For the module containing the active accumulator. */ +#define PFX MODB /* For the module containing the prefix registers. */ +#define IP MODC /* For the module containing the instruction pointer register. */ +#define SPIV MODD /* For the module containing the stack pointer and the interrupt vector. */ +#define LC MODD /* For the module containing the loop counters and HILO registers. */ +#define DP MODF /* For the module containig the data pointer registers. */ + +/* Register Types. */ +typedef enum _Reg_type +{ Reg_8R, /* 8 bit register. read only. */ + Reg_16R, /* 16 bit register, read only. */ + Reg_8W, /* 8 bit register, both read and write. */ + Reg_16W /* 16 bit register, both read and write. */ +} +Reg_type; + +/* Register Structure. */ +typedef struct reg +{ + char *reg_name; /* Register name. */ + short int Mod_name; /* The module name. */ + short int Mod_index; /* The module index. */ + int opcode; /* The opcode of the register. */ + Reg_type rtype; /* 8 bit/16 bit and read only/read write. */ + int arch; /* The Machine architecture. */ +} +reg_entry; + +reg_entry *new_reg_table = NULL; +int num_of_reg = 0; + +typedef struct +{ + char *rname; + int rindex; +} +reg_index; + +/* Register Table description. */ +reg_entry system_reg_table[] = +{ + /* Serial Registers */ + /* MODULE 8 Registers : I call them the control registers. */ + /* Accumulator Pointer CTRL[0h] */ + { + "AP", CTRL, 0x0, 0x00 | CTRL, Reg_8W, MAX}, + /* Accumulator Pointer Control Register : CTRL[1h] */ + + { + "APC", CTRL, 0x1, 0x10 | CTRL, Reg_8W, MAX}, + /* Processor Status Flag Register CTRL[4h] Note: Bits 6 and 7 read only */ + { + "PSF", CTRL, 0x4, 0x40 | CTRL, Reg_8W, MAX}, + /* Interrupt and Control Register : CTRL[5h] */ + { + "IC", CTRL, 0x5, 0x50 | CTRL, Reg_8W, MAX}, + /* Interrupt Mask Register : CTRL[6h] */ + { + "IMR", CTRL, 0x6, 0x60 | CTRL, Reg_8W, MAX}, + /* Interrupt System Control : CTRL[8h] */ + { + "SC", CTRL, 0x8, 0x80 | CTRL, Reg_8W, MAX}, + /* Interrupt Identification Register : CTRL[Bh] */ + { + "IIR", CTRL, 0xb, 0xb0 | CTRL, Reg_8R, MAX}, + /* System Clock Control Register : CTRL[Eh] Note: Bit 5 is read only */ + { + "CKCN", CTRL, 0xe, 0xe0 | CTRL, Reg_8W, MAX}, + /* Watchdog Control Register : CTRL[Fh] */ + { + "WDCN", CTRL, 0xf, 0xf0 | CTRL, Reg_8W, MAX}, + /* The 16 accumulator registers : ACC[0h-Fh] */ + { + "A[0]", ACC, 0x0, 0x00 | ACC, Reg_16W, MAXQ20}, + { + "A[1]", ACC, 0x1, 0x10 | ACC, Reg_16W, MAXQ20}, + { + "A[2]", ACC, 0x2, 0x20 | ACC, Reg_16W, MAXQ20}, + { + "A[3]", ACC, 0x3, 0x30 | ACC, Reg_16W, MAXQ20}, + { + "A[4]", ACC, 0x4, 0x40 | ACC, Reg_16W, MAXQ20}, + { + "A[5]", ACC, 0x5, 0x50 | ACC, Reg_16W, MAXQ20}, + { + "A[6]", ACC, 0x6, 0x60 | ACC, Reg_16W, MAXQ20}, + { + "A[7]", ACC, 0x7, 0x70 | ACC, Reg_16W, MAXQ20}, + { + "A[8]", ACC, 0x8, 0x80 | ACC, Reg_16W, MAXQ20}, + { + "A[9]", ACC, 0x9, 0x90 | ACC, Reg_16W, MAXQ20}, + { + "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_16W, MAXQ20}, + { + "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_16W, MAXQ20}, + { + "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_16W, MAXQ20}, + { + "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_16W, MAXQ20}, + { + "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_16W, MAXQ20}, + { + "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_16W, MAXQ20}, + /* The Active Accumulators : Act_Acc[0h-1h] */ + { + "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_16W, MAXQ20}, + { + "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_16W, MAXQ20}, + /* The 16 accumulator registers : ACC[0h-Fh] */ + { + "A[0]", ACC, 0x0, 0x00 | ACC, Reg_8W, MAXQ10}, + { + "A[1]", ACC, 0x1, 0x10 | ACC, Reg_8W, MAXQ10}, + { + "A[2]", ACC, 0x2, 0x20 | ACC, Reg_8W, MAXQ10}, + { + "A[3]", ACC, 0x3, 0x30 | ACC, Reg_8W, MAXQ10}, + { + "A[4]", ACC, 0x4, 0x40 | ACC, Reg_8W, MAXQ10}, + { + "A[5]", ACC, 0x5, 0x50 | ACC, Reg_8W, MAXQ10}, + { + "A[6]", ACC, 0x6, 0x60 | ACC, Reg_8W, MAXQ10}, + { + "A[7]", ACC, 0x7, 0x70 | ACC, Reg_8W, MAXQ10}, + { + "A[8]", ACC, 0x8, 0x80 | ACC, Reg_8W, MAXQ10}, + { + "A[9]", ACC, 0x9, 0x90 | ACC, Reg_8W, MAXQ10}, + { + "A[10]", ACC, 0xa, 0xa0 | ACC, Reg_8W, MAXQ10}, + { + "A[11]", ACC, 0xb, 0xb0 | ACC, Reg_8W, MAXQ10}, + { + "A[12]", ACC, 0xc, 0xc0 | ACC, Reg_8W, MAXQ10}, + { + "A[13]", ACC, 0xd, 0xd0 | ACC, Reg_8W, MAXQ10}, + { + "A[14]", ACC, 0xe, 0xe0 | ACC, Reg_8W, MAXQ10}, + { + "A[15]", ACC, 0xf, 0xf0 | ACC, Reg_8W, MAXQ10}, + /* The Active Accumulators : Act_Acc[0h-1h] */ + { + "A[AP]", Act_ACC, 0x1, 0x10 | Act_ACC, Reg_8W, MAXQ10}, + /* The Active Accumulators : Act_Acc[0h-1h] */ + { + "ACC", Act_ACC, 0x0, 0x00 | Act_ACC, Reg_8W, MAXQ10}, + /* The Prefix Registers : PFX[0h,2h] */ + { + "PFX[0]", PFX, 0x0, 0x00 | PFX, Reg_16W, MAX}, + { + "PFX[1]", PFX, 0x1, 0x10 | PFX, Reg_16W, MAX}, + { + "PFX[2]", PFX, 0x2, 0x20 | PFX, Reg_16W, MAX}, + { + "PFX[3]", PFX, 0x3, 0x30 | PFX, Reg_16W, MAX}, + { + "PFX[4]", PFX, 0x4, 0x40 | PFX, Reg_16W, MAX}, + { + "PFX[5]", PFX, 0x5, 0x50 | PFX, Reg_16W, MAX}, + { + "PFX[6]", PFX, 0x6, 0x60 | PFX, Reg_16W, MAX}, + { + "PFX[7]", PFX, 0x7, 0x70 | PFX, Reg_16W, MAX}, + /* The Instruction Pointer Registers : IP[0h,8h] */ + { + "IP", IP, 0x0, 0x00 | IP, Reg_16W, MAX}, + /* The Stack Pointer Registers : SPIV[1h,9h] */ + { + "SP", SPIV, 0x1, 0x10 | SPIV, Reg_16W, MAX}, + /* The Interrupt Vector Registers : SPIV[2h,Ah] */ + { + "IV", SPIV, 0x2, 0x20 | SPIV, Reg_16W, MAX}, + /* ADDED for New Specification */ + + /* The Loop Counter Registers : LCHILO[0h-4h,8h-Bh] */ + { + "LC[0]", LC, 0x6, 0x60 | LC, Reg_16W, MAX}, + { + "LC[1]", LC, 0x7, 0x70 | LC, Reg_16W, MAX}, + /* MODULE Eh Whole Column has changed */ + + { + "OFFS", MODE, 0x3, 0x30 | MODE, Reg_8W, MAX}, + { + "DPC", MODE, 0x4, 0x40 | MODE, Reg_16W, MAX}, + { + "GR", MODE, 0x5, 0x50 | MODE, Reg_16W, MAX}, + { + "GRL", MODE, 0x6, 0x60 | MODE, Reg_8W, MAX}, + { + "BP", MODE, 0x7, 0x70 | MODE, Reg_16W, MAX}, + { + "GRS", MODE, 0x8, 0x80 | MODE, Reg_16W, MAX}, + { + "GRH", MODE, 0x9, 0x90 | MODE, Reg_8W, MAX}, + { + "GRXL", MODE, 0xA, 0xA0 | MODE, Reg_8R, MAX}, + { + "FP", MODE, 0xB, 0xB0 | MODE, Reg_16R, MAX}, + /* The Data Pointer registers : DP[3h,7h,Bh,Fh] */ + { + "DP[0]", DP, 0x3, 0x30 | DP, Reg_16W, MAX}, + { + "DP[1]", DP, 0x7, 0x70 | DP, Reg_16W, MAX}, +}; +typedef struct +{ + char *name; + int type; +} +match_table; + +#define GPIO0 0x00 /* Gerneral Purpose I/O Module 0. */ +#define GPIO1 0x01 /* Gerneral Purpose I/O Module 1. */ +#define RTC 0x00 /* Real Time Clock Module. */ +#define MAC 0x02 /* Hardware Multiplier Module. */ +#define SER0 0x02 /* Contains the UART Registers. */ +#define SPI 0x03 /* Serial Pheripheral Interface Module. */ +#define OWBM 0x03 /* One Wire Bus Module. */ +#define SER1 0x03 /* Contains the UART Registers. */ +#define TIMER20 0x03 /* Timer Counter Module 2. */ +#define TIMER21 0x04 /* Timer Counter Module 2. */ +#define JTAGD 0x03 /* In-Circuit Debugging Support. */ +#define LCD 0x03 /* LCD register Modules. */ + +/* Plugable modules register table f. */ + +reg_entry peripheral_reg_table[] = +{ + /* -------- The GPIO Module Registers -------- */ + /* Port n Output Registers : GPIO[0h-4h] */ + { + "PO0", GPIO0, 0x0, 0x00 | MOD0, Reg_8W, MAX}, + { + "PO1", GPIO0, 0x1, 0x10 | MOD0, Reg_8W, MAX}, + { + "PO2", GPIO0, 0x2, 0x20 | MOD0, Reg_8W, MAX}, + { + "PO3", GPIO0, 0x3, 0x30 | MOD0, Reg_8W, MAX}, + /* External Interrupt Flag Register : GPIO[6h] */ + { + "EIF0", GPIO0, 0x6, 0x60 | MOD0, Reg_8W, MAX}, + /* External Interrupt Enable Register : GPIO[7h] */ + { + "EIE0", GPIO0, 0x7, 0x70 | MOD0, Reg_8W, MAX}, + /* Port n Input Registers : GPIO[8h-Bh] */ + { + "PI0", GPIO0, 0x8, 0x80 | MOD0, Reg_8W, MAX}, + { + "PI1", GPIO0, 0x9, 0x90 | MOD0, Reg_8W, MAX}, + { + "PI2", GPIO0, 0xa, 0xa0 | MOD0, Reg_8W, MAX}, + { + "PI3", GPIO0, 0xb, 0xb0 | MOD0, Reg_8W, MAX}, + { + "EIES0", GPIO0, 0xc, 0xc0 | MOD0, Reg_8W, MAX}, + /* Port n Direction Registers : GPIO[Ch-Fh] */ + { + "PD0", GPIO0, 0x10, 0x10 | MOD0, Reg_8W, MAX}, + { + "PD1", GPIO0, 0x11, 0x11 | MOD0, Reg_8W, MAX}, + { + "PD2", GPIO0, 0x12, 0x12 | MOD0, Reg_8W, MAX}, + { + "PD3", GPIO0, 0x13, 0x13 | MOD0, Reg_8W, MAX}, + /* -------- Real Time Counter Module RTC -------- */ + /* RTC Control Register : [01h] */ + { + "RCNT", RTC, 0x19, 0x19 | MOD0, Reg_16W, MAX}, + /* RTC Seconds High [02h] */ + { + "RTSS", RTC, 0x1A, 0x1A | MOD0, Reg_8W, MAX}, + /* RTC Seconds Low [03h] */ + { + "RTSH", RTC, 0x1b, 0x1b | MOD0, Reg_16W, MAX}, + /* RTC Subsecond Register [04h] */ + { + "RTSL", RTC, 0x1C, 0x1C | MOD0, Reg_16W, MAX}, + /* RTC Alarm seconds high [05h] */ + { + "RSSA", RTC, 0x1D, 0x1D | MOD0, Reg_8W, MAX}, + /* RTC Alarm seconds high [06h] */ + { + "RASH", RTC, 0x1E, 0x1E | MOD0, Reg_8W, MAX}, + /* RTC Subsecond Alarm Register [07h] */ + { + "RASL", RTC, 0x1F, 0x1F | MOD0, Reg_16W, MAX}, + /* -------- The GPIO Module Registers -------- */ + /* Port n Output Registers : GPIO[0h-4h] */ + { + "PO4", GPIO1, 0x0, 0x00 | MOD1, Reg_8W, MAX}, + { + "PO5", GPIO1, 0x1, 0x10 | MOD1, Reg_8W, MAX}, + { + "PO6", GPIO1, 0x2, 0x20 | MOD1, Reg_8W, MAX}, + { + "PO7", GPIO1, 0x3, 0x30 | MOD1, Reg_8W, MAX}, + /* External Interrupt Flag Register : GPIO[6h] */ + { + "EIF1", GPIO0, 0x6, 0x60 | MOD1, Reg_8W, MAX}, + /* External Interrupt Enable Register : GPIO[7h] */ + { + "EIE1", GPIO0, 0x7, 0x70 | MOD1, Reg_8W, MAX}, + /* Port n Input Registers : GPIO[8h-Bh] */ + { + "PI4", GPIO1, 0x8, 0x80 | MOD1, Reg_8W, MAX}, + { + "PI5", GPIO1, 0x9, 0x90 | MOD1, Reg_8W, MAX}, + { + "PI6", GPIO1, 0xa, 0xa0 | MOD1, Reg_8W, MAX}, + { + "PI7", GPIO1, 0xb, 0xb0 | MOD1, Reg_8W, MAX}, + { + "EIES1", GPIO1, 0xc, 0xc0 | MOD1, Reg_8W, MAX}, + /* Port n Direction Registers : GPIO[Ch-Fh] */ + { + "PD4", GPIO1, 0x10, 0x10 | MOD1, Reg_8W, MAX}, + { + "PD5", GPIO1, 0x11, 0x11 | MOD1, Reg_8W, MAX}, + { + "PD6", GPIO1, 0x12, 0x12 | MOD1, Reg_8W, MAX}, + { + "PD7", GPIO1, 0x13, 0x13 | MOD1, Reg_8W, MAX}, +#if 0 + /* Supply Boltage Check Register */ + { + "SVS", GPIO1, 0x1e, 0x1e | GPIO1, Reg_8W, MAX}, + /* Wake up output register */ + { + "WK0", GPIO1, 0x1f, 0x1f | GPIO1, Reg_8W, MAX}, +#endif /* */ + + /* -------- MAC Hardware multiplier module -------- */ + /* MAC Hardware Multiplier control register: [01h] */ + { + "MCNT", MAC, 0x1, 0x10 | MOD2, Reg_8W, MAX}, + /* MAC Multiplier Operand A Register [02h] */ + { + "MA", MAC, 0x2, 0x20 | MOD2, Reg_16W, MAX}, + /* MAC Multiplier Operand B Register [03h] */ + { + "MB", MAC, 0x3, 0x30 | MOD2, Reg_16W, MAX}, + /* MAC Multiplier Accumulator 2 Register [04h] */ + { + "MC2", MAC, 0x4, 0x40 | MOD2, Reg_16W, MAX}, + /* MAC Multiplier Accumulator 1 Register [05h] */ + { + "MC1", MAC, 0x5, 0x50 | MOD2, Reg_16W, MAX}, + /* MAC Multiplier Accumulator 0 Register [06h] */ + { + "MC0", MAC, 0x6, 0x60 | MOD2, Reg_16W, MAX}, + /* -------- The Serial I/O module SER -------- */ + /* UART registers */ + /* Serial Port Control Register : SER[6h] */ + { + "SCON0", SER0, 0x6, 0x60 | MOD2, Reg_8W, MAX}, + /* Serial Data Buffer Register : SER[7h] */ + { + "SBUF0", SER0, 0x7, 0x70 | MOD2, Reg_8W, MAX}, + /* Serial Port Mode Register : SER[4h] */ + { + "SMD0", SER0, 0x8, 0x80 | MOD2, Reg_8W, MAX}, + /* Serial Port Phase Register : SER[4h] */ + { + "PR0", SER1, 0x9, 0x90 | MOD2, Reg_16W, MAX}, + /* ------ LCD Display Module ---------- */ + { + "LCRA", LCD, 0xd, 0xd0 | MOD2, Reg_16W, MAX}, + { + "LCFG", LCD, 0xe, 0xe0 | MOD2, Reg_8W, MAX}, + { + "LCD16", LCD, 0xf, 0xf0 | MOD2, Reg_8W, MAX}, + { + "LCD0", LCD, 0x10, 0x10 | MOD2, Reg_8W, MAX}, + { + "LCD1", LCD, 0x11, 0x11 | MOD2, Reg_8W, MAX}, + { + "LCD2", LCD, 0x12, 0x12 | MOD2, Reg_8W, MAX}, + { + "LCD3", LCD, 0x13, 0x13 | MOD2, Reg_8W, MAX}, + { + "LCD4", LCD, 0x14, 0x14 | MOD2, Reg_8W, MAX}, + { + "LCD5", LCD, 0x15, 0x15 | MOD2, Reg_8W, MAX}, + { + "LCD6", LCD, 0x16, 0x16 | MOD2, Reg_8W, MAX}, + { + "LCD7", LCD, 0x17, 0x17 | MOD2, Reg_8W, MAX}, + { + "LCD8", LCD, 0x18, 0x18 | MOD2, Reg_8W, MAX}, + { + "LCD9", LCD, 0x19, 0x19 | MOD2, Reg_8W, MAX}, + { + "LCD10", LCD, 0x1a, 0x1a | MOD2, Reg_8W, MAX}, + { + "LCD11", LCD, 0x1b, 0x1b | MOD2, Reg_8W, MAX}, + { + "LCD12", LCD, 0x1c, 0x1c | MOD2, Reg_8W, MAX}, + { + "LCD13", LCD, 0x1d, 0x1d | MOD2, Reg_8W, MAX}, + { + "LCD14", LCD, 0x1e, 0x1e | MOD2, Reg_8W, MAX}, + { + "LCD15", LCD, 0x1f, 0x1f | MOD2, Reg_8W, MAX}, + /* -------- SPI registers -------- */ + /* SPI data buffer Register : SER[7h] */ + { + "SPIB", SPI, 0x5, 0x50 | MOD3, Reg_16W, MAX}, + /* SPI Control Register : SER[8h] Note : Bit 7 is a read only bit */ + { + "SPICN", SPI, 0x15, 0x15 | MOD3, Reg_8W, MAX}, + /* SPI Configuration Register : SER[9h] Note : Bits 4,3 and 2 are read + only. */ + { + "SPICF", SPI, 0x16, 0x16 | MOD3, Reg_8W, MAX}, + /* SPI Clock Register : SER[Ah] */ + { + "SPICK", SPI, 0x17, 0x17 | MOD3, Reg_8W, MAX}, + /* -------- One Wire Bus Master OWBM -------- */ + /* OWBM One Wire address Register register: [01h] */ + { + "OWA", OWBM, 0x13, 0x13 | MOD3, Reg_8W, MAX}, + /* OWBM One Wire Data register: [02h] */ + { + "OWD", OWBM, 0x14, 0x14 | MOD3, Reg_8W, MAX}, + /* -------- The Serial I/O module SER -------- */ + /* UART registers */ + /* Serial Port Control Register : SER[6h] */ + { + "SCON1", SER1, 0x6, 0x60 | MOD3, Reg_8W, MAX}, + /* Serial Data Buffer Register : SER[7h] */ + { + "SBUF1", SER1, 0x7, 0x70 | MOD3, Reg_8W, MAX}, + /* Serial Port Mode Register : SER[4h] */ + { + "SMD1", SER1, 0x8, 0x80 | MOD3, Reg_8W, MAX}, + /* Serial Port Phase Register : SER[4h] */ + { + "PR1", SER1, 0x9, 0x90 | MOD3, Reg_16W, MAX}, + /* -------- Timer/Counter 2 Module -------- */ + /* Timer 2 configuration Register : TC[3h] */ + { + "T2CNA0", TIMER20, 0x0, 0x00 | MOD3, Reg_8W, MAX}, + { + "T2H0", TIMER20, 0x1, 0x10 | MOD3, Reg_8W, MAX}, + { + "T2RH0", TIMER20, 0x2, 0x20 | MOD3, Reg_8W, MAX}, + { + "T2CH0", TIMER20, 0x3, 0x30 | MOD3, Reg_8W, MAX}, + { + "T2CNB0", TIMER20, 0xc, 0xc0 | MOD3, Reg_8W, MAX}, + { + "T2V0", TIMER20, 0xd, 0xd0 | MOD3, Reg_16W, MAX}, + { + "T2R0", TIMER20, 0xe, 0xe0 | MOD3, Reg_16W, MAX}, + { + "T2C0", TIMER20, 0xf, 0xf0 | MOD3, Reg_16W, MAX}, + { + "T2CFG0", TIMER20, 0x10, 0x10 | MOD3, Reg_8W, MAX}, + /* Timer 2-1 configuration Register : TC[4h] */ + + { + "T2CNA1", TIMER21, 0x0, 0x00 | MOD4, Reg_8W, MAX}, + { + "T2H1", TIMER21, 0x1, 0x10 | MOD4, Reg_8W, MAX}, + { + "T2RH1", TIMER21, 0x2, 0x20 | MOD4, Reg_8W, MAX}, + { + "T2CH1", TIMER21, 0x3, 0x30 | MOD4, Reg_8W, MAX}, + { + "T2CNA2", TIMER21, 0x4, 0x40 | MOD4, Reg_8W, MAX}, + { + "T2H2", TIMER21, 0x5, 0x50 | MOD4, Reg_8W, MAX}, + { + "T2RH2", TIMER21, 0x6, 0x60 | MOD4, Reg_8W, MAX}, + { + "T2CH2", TIMER21, 0x7, 0x70 | MOD4, Reg_8W, MAX}, + { + "T2CNB1", TIMER21, 0x8, 0x80 | MOD4, Reg_8W, MAX}, + { + "T2V1", TIMER21, 0x9, 0x90 | MOD4, Reg_16W, MAX}, + { + "T2R1", TIMER21, 0xa, 0xa0 | MOD4, Reg_16W, MAX}, + { + "T2C1", TIMER21, 0xb, 0xb0 | MOD4, Reg_16W, MAX}, + { + "T2CNB2", TIMER21, 0xc, 0xc0 | MOD4, Reg_8W, MAX}, + { + "T2V2", TIMER21, 0xd, 0xd0 | MOD4, Reg_16W, MAX}, + { + "T2R2", TIMER21, 0xe, 0xe0 | MOD4, Reg_16W, MAX}, + { + "T2C2", TIMER21, 0xf, 0xf0 | MOD4, Reg_16W, MAX}, + { + "T2CFG1", TIMER21, 0x10, 0x10 | MOD4, Reg_8W, MAX}, + { + "T2CFG2", TIMER21, 0x11, 0x11 | MOD4, Reg_8W, MAX}, + { + NULL, 0, 0, 0, 0, 0} +}; + +/* Memory access argument. */ +struct mem_access +{ + char *name; /* Name of the Memory access operand. */ + int opcode; /* Its corresponding opcode. */ +}; +typedef struct mem_access mem_access; + +/* The Memory table for accessing the data memory through particular registers. */ +struct mem_access mem_table[] = +{ + /* The Pop Operation on the stack. */ + {"@SP--", 0x0d}, + /* Data Pointer 0 */ + {"@DP[0]", 0x0f}, + /* Data Ponter 1 */ + {"@DP[1]", 0x4f}, + /* Data Pointer 0 post increment */ + {"@DP[0]++", 0x1f}, + /* Data Pointer 1 post increment */ + {"@DP[1]++", 0x5f}, + /* Data Pointer 0 post decrement */ + {"@DP[0]--", 0x2f}, + /* Data Pointer 1 post decrement */ + {"@DP[1]--", 0x6f}, + /* ADDED According to New Specification. */ + + {"@BP[OFFS]", 0x0E}, + {"@BP[OFFS++]", 0x1E}, + {"@BP[OFFS--]", 0x2E}, + {"NUL", 0x76}, + {"@++SP", 0x0D}, + {"@BP[++OFFS]", 0x1E}, + {"@BP[--OFFS]", 0x2E}, + {"@++DP[0]", 0x1F}, + {"@++DP[1]", 0x5F}, {"@--DP[0]", 0x2F}, {"@--DP[1]", 0x6F} +}; + +/* Register bit argument. */ +struct reg_bit +{ + reg_entry *reg; + int bit; +}; +typedef struct reg_bit reg_bit; + +/* There are certain names given to particular bits of some registers. + These will be taken care of here. */ +struct bit_name +{ + char *name; + char *reg_bit; +}; +typedef struct bit_name bit_name; + +bit_name bit_table[] = +{ + { + "RI", "SCON.0"}, + /* FOr APC */ + { + "MOD0", "APC.0"}, + { + "MOD1", "APC.1"}, + { + "MOD2", "APC.2"}, + { + "IDS", "APC.6"}, + { + "CLR", "APC.6"}, + /* For PSF */ + { + "E", "PSF.0"}, + { + "C", "PSF.1"}, + { + "OV", "PSF.2"}, + { + "S", "PSF.6"}, + { + "Z", "PSF.7"}, + /* For IC */ + + { + "IGE", "IC.0"}, + { + "INS", "IC.1"}, + { + "CGDS", "IC.5"}, + /* For IMR */ + + { + "IM0", "IMR.0"}, + { + "IM1", "IMR.1"}, + { + "IM2", "IMR.2"}, + { + "IM3", "IMR.3"}, + { + "IM4", "IMR.4"}, + { + "IM5", "IMR.5"}, + { + "IMS", "IMR.7"}, + /* For SC */ + { + "PWL", "SC.1"}, + { + "ROD", "SC.2"}, + { + "UPA", "SC.3"}, + { + "CDA0", "SC.4"}, + { + "CDA1", "SC.5"}, + /* For IIR */ + + { + "II0", "IIR.0"}, + { + "II1", "IIR.1"}, + { + "II2", "IIR.2"}, + { + "II3", "IIR.3"}, + { + "II4", "IIR.4"}, + { + "II5", "IIR.5"}, + { + "IIS", "IIR.7"}, + /* For CKCN */ + + { + "CD0", "CKCN.0"}, + { + "CD1", "CKCN.1"}, + { + "PMME", "CKCN.2"}, + { + "SWB", "CKCN.3"}, + { + "STOP", "CKCN.4"}, + { + "RGMD", "CKCN.5"}, + { + "RGSL", "CKCN.6"}, + /* For WDCN */ + + { + "RWT", "WDCN.0"}, + { + "EWT", "WDCN.1"}, + { + "WTRF", "WDCN.2"}, + { + "WDIF", "WDCN.3"}, + { + "WD0", "WDCN.4"}, + { + "WD1", "WDCN.5"}, + { + "EWDI", "WDCN.6"}, + { + "POR", "WDCN.7"}, + /* For DPC */ + + { + "DPS0", "DPC.0"}, + { + "DPS1", "DPC.1"}, + { + "WBS0", "DPC.2"}, + { + "WBS1", "DPC.3"}, + { + "WBS2", "DPC.4"}, + + /* For SCON */ + { + "TI", "SCON.1"}, + { + "RB8", "SCON.2"}, + { + "TB8", "SCON.3"}, + { + "REN", "SCON.4"}, + { + "SM2", "SCON.5"}, + { + "SM1", "SCON.6"}, + { + "SM0", "SCON.7"}, + { + "FE", "SCON.7"} +}; + +const char *LSInstr[] = +{ + "LJUMP", "SJUMP", "LDJNZ", "SDJNZ", "LCALL", "SCALL", "JUMP", + "DJNZ", "CALL", NULL +}; + +typedef enum +{ + DST, + SRC, + BOTH, +} +type1; + +struct mem_access_syntax +{ + char name[12]; /* Name of the Memory access operand. */ + type1 type; + char *invalid_op[5]; +}; +typedef struct mem_access_syntax mem_access_syntax; + +/* The Memory Access table for accessing the data memory through particular + registers. */ +const mem_access_syntax mem_access_syntax_table[] = +{ + { + "@SP--", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + /* Data Pointer 0 */ + { + "@DP[0]", BOTH, + { + "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}}, + /* Data Ponter 1 */ + { + "@DP[1]", BOTH, + { + "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}}, + /* Data Pointer 0 post increment */ + { + "@DP[0]++", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + /* Data Pointer 1 post increment */ + { + "@DP[1]++", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + /* Data Pointer 0 post decrement */ + { + "@DP[0]--", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + /* Data Pointer 1 post decrement */ + { + "@DP[1]--", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + /* ADDED According to New Specification */ + + { + "@BP[OFFS]", BOTH, + { + "@BP[OFFS++]", "@BP[OFFS--]", NULL, NULL, NULL}}, + { + "@BP[OFFS++]", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + { + "@BP[OFFS--]", SRC, + { + NULL, NULL, NULL, NULL, NULL}}, + { + "NUL", DST, + { + NULL, NULL, NULL, NULL, NULL}}, + { + "@++SP", DST, + { + NULL, NULL, NULL, NULL, NULL}}, + { + "@BP[++OFFS]", DST, + { + "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}}, + { + "@BP[--OFFS]", DST, + { + "@BP[OFFS--]", "@BP[OFFS++]", NULL, NULL, NULL}}, + { + "@++DP[0]", DST, + { + "@DP[0]--", "@DP[0]++", NULL, NULL, NULL}}, + { + "@++DP[1]", DST, + { + "@DP[1]--", "@DP[1]++", NULL, NULL, NULL}}, + { + "@--DP[0]", DST, + { + "@DP[0]++", "@DP[0]--", NULL, NULL, NULL}}, + { + "@--DP[1]", DST, + { + "@DP[1]++", "@DP[1]--", NULL, NULL, NULL}} +}; + +#endif diff --git a/gnu/dist/binutils/include/opcode/mips.h b/gnu/dist/binutils/include/opcode/mips.h index 5c3ddfcd7b5..a71ca475909 100644 --- a/gnu/dist/binutils/include/opcode/mips.h +++ b/gnu/dist/binutils/include/opcode/mips.h @@ -1,5 +1,6 @@ /* mips.h. Mips opcode list for GDB, the GNU debugger. - Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 + Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, + 2003, 2004, 2005 Free Software Foundation, Inc. Contributed by Ralph Campbell and OSF Commented and modified by Ian Lance Taylor, Cygnus Support @@ -192,6 +193,8 @@ struct mips_opcode of bits describing the instruction, notably any relevant hazard information. */ unsigned long pinfo; + /* A collection of additional bits describing the instruction. */ + unsigned long pinfo2; /* A collection of bits describing the instruction sets of which this instruction or macro is a member. */ unsigned long membership; @@ -376,10 +379,16 @@ struct mips_opcode #define INSN_MULT 0x40000000 /* Instruction synchronize shared memory. */ #define INSN_SYNC 0x80000000 -/* Instruction reads MDMX accumulator. XXX FIXME: No bits left! */ -#define INSN_READ_MDMX_ACC 0 -/* Instruction writes MDMX accumulator. XXX FIXME: No bits left! */ -#define INSN_WRITE_MDMX_ACC 0 + +/* These are the bits which may be set in the pinfo2 field of an + instruction. */ + +/* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */ +#define INSN2_ALIAS 0x00000001 +/* Instruction reads MDMX accumulator. */ +#define INSN2_READ_MDMX_ACC 0x00000002 +/* Instruction writes MDMX accumulator. */ +#define INSN2_WRITE_MDMX_ACC 0x00000004 /* Instruction is actually a macro. It should be ignored by the disassembler, and requires special treatment by the assembler. */ @@ -470,6 +479,7 @@ struct mips_opcode #define CPU_R6000 6000 #define CPU_RM7000 7000 #define CPU_R8000 8000 +#define CPU_RM9000 9000 #define CPU_R10000 10000 #define CPU_R12000 12000 #define CPU_MIPS16 16 @@ -489,6 +499,7 @@ struct mips_opcode (((insn)->membership & isa) != 0 \ || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \ + || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \ || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \ || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \ || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \ diff --git a/gnu/dist/binutils/include/opcode/mn10300.h b/gnu/dist/binutils/include/opcode/mn10300.h index bd7faa110aa..a2e7784e992 100644 --- a/gnu/dist/binutils/include/opcode/mn10300.h +++ b/gnu/dist/binutils/include/opcode/mn10300.h @@ -1,5 +1,5 @@ /* mn10300.h -- Header file for Matsushita 10300 opcode table - Copyright 1996, 1997, 1998, 1999 Free Software Foundation, Inc. + Copyright 1996, 1997, 1998, 1999, 2003 Free Software Foundation, Inc. Written by Jeff Law, Cygnus Support This file is part of GDB, GAS, and the GNU binutils. diff --git a/gnu/dist/binutils/include/opcode/msp430.h b/gnu/dist/binutils/include/opcode/msp430.h index 19702254eef..dc3604ce883 100644 --- a/gnu/dist/binutils/include/opcode/msp430.h +++ b/gnu/dist/binutils/include/opcode/msp430.h @@ -1,6 +1,6 @@ /* Opcode table for the TI MSP430 microcontrollers - Copyright 2002 Free Software Foundation, Inc. + Copyright 2002, 2004 Free Software Foundation, Inc. Contributed by Dmitry Diky <diwil@mail.ru> This program is free software; you can redistribute it and/or modify @@ -103,6 +103,20 @@ static struct msp430_opcode_s msp430_opcodes[] = MSP_INSN (rra, 2, 1, 0x1100, 0xff80), MSP_INSN (swpb, 2, 1, 0x1080, 0xffc0), MSP_INSN (rrc, 2, 1, 0x1000, 0xff80), + /* Simple polymorphs. */ + MSP_INSN (beq, 4, 0, 0, 0xffff), + MSP_INSN (bne, 4, 1, 0, 0xffff), + MSP_INSN (blt, 4, 2, 0, 0xffff), + MSP_INSN (bltu, 4, 3, 0, 0xffff), + MSP_INSN (bge, 4, 4, 0, 0xffff), + MSP_INSN (bgeu, 4, 5, 0, 0xffff), + MSP_INSN (bltn, 4, 6, 0, 0xffff), + MSP_INSN (jump, 4, 7, 0, 0xffff), + /* Long polymorphs. */ + MSP_INSN (bgt, 5, 0, 0, 0xffff), + MSP_INSN (bgtu, 5, 1, 0, 0xffff), + MSP_INSN (bleu, 5, 2, 0, 0xffff), + MSP_INSN (ble, 5, 3, 0, 0xffff), /* End of instruction set. */ { NULL, 0, 0, 0, 0 } diff --git a/gnu/dist/binutils/include/opcode/ppc.h b/gnu/dist/binutils/include/opcode/ppc.h index d55caa7568f..a21cc301e82 100644 --- a/gnu/dist/binutils/include/opcode/ppc.h +++ b/gnu/dist/binutils/include/opcode/ppc.h @@ -249,7 +249,7 @@ extern const struct powerpc_operand powerpc_operands[]; #define PPC_OPERAND_ABSOLUTE (01000) /* This operand is optional, and is zero if omitted. This is used for - the optional BF and L fields in the comparison instructions. The + example, in the optional BF field in the comparison instructions. The assembler must count the number of operands remaining on the line, and the number of operands remaining for the opcode, and decide whether this operand is present or not. The disassembler should diff --git a/gnu/dist/binutils/include/opcode/s390.h b/gnu/dist/binutils/include/opcode/s390.h index f582a4e5104..54648f998bf 100644 --- a/gnu/dist/binutils/include/opcode/s390.h +++ b/gnu/dist/binutils/include/opcode/s390.h @@ -1,5 +1,5 @@ /* s390.h -- Header file for S390 opcode table - Copyright 2000, 2001 Free Software Foundation, Inc. + Copyright 2000, 2001, 2003 Free Software Foundation, Inc. Contributed by Martin Schwidefsky (schwidefsky@de.ibm.com). This file is part of BFD, the Binary File Descriptor library. diff --git a/gnu/dist/binutils/include/opcode/tic54x.h b/gnu/dist/binutils/include/opcode/tic54x.h index ae657225d61..a7958dc9ce0 100644 --- a/gnu/dist/binutils/include/opcode/tic54x.h +++ b/gnu/dist/binutils/include/opcode/tic54x.h @@ -1,5 +1,5 @@ /* tic54x.h -- Header file for TI TMS320C54X opcode table - Copyright 1999, 2000 Free Software Foundation, Inc. + Copyright 1999, 2000, 2001 Free Software Foundation, Inc. Written by Timothy Wall (twall@cygnus.com) This file is part of GDB, GAS, and the GNU binutils. |
