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authortv <tv@NetBSD.org>1999-02-02 19:51:16 +0000
committertv <tv@NetBSD.org>1999-02-02 19:51:16 +0000
commit2e8b57510c512922b01977bf9c07cb986ddbaa67 (patch)
tree99f0ff2ba55134ad127492d887b5b6567773ef25 /gnu/dist/include/opcode/mips.h
parent269cb58003ce63bbb1763517287a25b909583ae4 (diff)
By popular demand, import binutils 2.9.1.
Diffstat (limited to 'gnu/dist/include/opcode/mips.h')
-rw-r--r--gnu/dist/include/opcode/mips.h64
1 files changed, 49 insertions, 15 deletions
diff --git a/gnu/dist/include/opcode/mips.h b/gnu/dist/include/opcode/mips.h
index 517aa096a8b..ee5ee82d3cb 100644
--- a/gnu/dist/include/opcode/mips.h
+++ b/gnu/dist/include/opcode/mips.h
@@ -120,7 +120,9 @@ Software Foundation, 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
#define OP_SH_MMI 0 /* Multimedia (parallel) op */
#define OP_MASK_MMI 0x3f
#define OP_SH_MMISUB 6
-#define OP_MASK_MMISUB 0x1f
+#define OP_MASK_MMISUB 0x1f
+#define OP_MASK_PERFREG 0x1f /* Performance monitoring */
+#define OP_SH_PERFREG 1
/* This structure holds information for a particular instruction. */
@@ -132,9 +134,7 @@ struct mips_opcode
const char *args;
/* The basic opcode for the instruction. When assembling, this
opcode is modified by the arguments to produce the actual opcode
- that is used. If pinfo is INSN_MACRO, then this is instead the
- ISA level of the macro (0 or 1 is always supported, 2 is ISA 2,
- etc.). */
+ that is used. If pinfo is INSN_MACRO, then this is 0. */
unsigned long match;
/* If pinfo is not INSN_MACRO, then this is a bit mask for the
relevant portions of the opcode when disassembling. If the
@@ -146,6 +146,9 @@ struct mips_opcode
of bits describing the instruction, notably any relevant hazard
information. */
unsigned long pinfo;
+ /* A collection of bits describing the instruction sets of which this
+ instruction or macro is a member. */
+ unsigned long membership;
};
/* These are the characters which may appears in the args field of an
@@ -192,6 +195,7 @@ struct mips_opcode
Coprocessor instructions:
"E" 5 bit target register (OP_*_RT)
"G" 5 bit destination register (OP_*_RD)
+ "P" 5 bit performance-monitor register (OP_*_PERFREG)
Macro instructions:
"A" General 32 bit expression
@@ -200,6 +204,15 @@ struct mips_opcode
"L" 64 bit floating point constant in .lit8
"f" 32 bit floating point constant
"l" 32 bit floating point constant in .lit4
+
+ Other:
+ "()" parens surrounding optional value
+ "," separates operands
+
+ Characters used so far, for quick reference when adding more:
+ "<>(),"
+ "ABCDEFGILMNSTRVW"
+ "abcdfhijkloprstuvwxz"
*/
/* These are the bits which may be set in the pinfo field of an
@@ -261,24 +274,45 @@ struct mips_opcode
#define INSN_TRAP 0x04000000
/* Instruction stores value into memory. */
#define INSN_STORE_MEMORY 0x08000000
+/* Instruction uses single precision floating point. */
+#define FP_S 0x10000000
+/* Instruction uses double precision floating point. */
+#define FP_D 0x20000000
+
+/* As yet unused bits: 0x40000000 */
+
+/* Instruction is actually a macro. It should be ignored by the
+ disassembler, and requires special treatment by the assembler. */
+#define INSN_MACRO 0xffffffff
+
+
+
+
+
/* MIPS ISA field--CPU level at which insn is supported. */
-#define INSN_ISA 0x70000000
+#define INSN_ISA 0x0000000F
+/* An instruction which is not part of any basic MIPS ISA.
+ (ie it is a chip specific instruction) */
+#define INSN_NO_ISA 0x00000000
+/* MIPS ISA 1 instruction. */
+#define INSN_ISA1 0x00000001
/* MIPS ISA 2 instruction (R6000 or R4000). */
-#define INSN_ISA2 0x10000000
+#define INSN_ISA2 0x00000002
/* MIPS ISA 3 instruction (R4000). */
-#define INSN_ISA3 0x20000000
-/* MIPS R4650 instruction. */
-#define INSN_4650 0x30000000
+#define INSN_ISA3 0x00000003
/* MIPS ISA 4 instruction (R8000). */
-#define INSN_ISA4 0x40000000
+#define INSN_ISA4 0x00000004
+
+/* Chip specific instructions. These are bitmasks. */
+/* MIPS R4650 instruction. */
+#define INSN_4650 0x00000010
/* LSI R4010 instruction. */
-#define INSN_4010 0x50000000
+#define INSN_4010 0x00000020
/* NEC VR4100 instruction. */
-#define INSN_4100 0x60000000
+#define INSN_4100 0x00000040
+/* Toshiba R3900 instruction. */
+#define INSN_3900 0x00000080
-/* Instruction is actually a macro. It should be ignored by the
- disassembler, and requires special treatment by the assembler. */
-#define INSN_MACRO 0xffffffff
/* This is a list of macro expanded instructions.
*