summaryrefslogtreecommitdiff
path: root/sys/arch/arm/cortex
AgeCommit message (Collapse)Author
2022-11-19G/C gtmr_init function declarationskrll
2022-11-05Handle speed change eventsjmcneill
2022-06-26build fix: remove includes of opt_gic.hjmcneill
2022-06-25gicv3: Treat all IPLs below IPL_VM as IPL_NONE for hwpl mappingsjmcneill
2022-06-25Remove GIC_SPLFUNCS.jmcneill
2022-06-25pic: Update ci_cpl in pic_set_priority callback.jmcneill
Not all ICs need interrupts disabled to update the priority. DAIF accesses are not cheap, so push the update of ci_cpl from pic_set_priority to the IC's pic_set_priority callback, and let the IC driver determine whether or not it needs interrupts disabled.
2022-03-28arm/cortex: Use container_of, not bespoke offsetof arithmetic.riastradh
2022-03-03arm: Use device_set_private for various drivers.riastradh
2022-01-02arm: Remove #ifdef DIAGNOSTIC now wrong after KASSERT change.riastradh
Objects in question aren't volatile here so access is flushable.
2021-11-13fix aarch64 buildjakllsch
2021-11-12gtmr: Add support for arm,cpu-registers-not-fw-configured property.jmcneill
On armv7, arm,cpu-registers-not-fw-configured means that firmware hasn't bothered to configure any generic timer registers and we need to initialize cntfrq ourselves.
2021-10-31Fix non-DIAGNOSTIC builds (hopefully). No idea why this didn't fail toskrll
build for me without DIAGNOSTIC.
2021-10-31Rework Arm (32bit and 64bit) AP startup so that cpu_hatch doesn't sleep.skrll
The AP initialisation code in cpu_init_secondary_processor will read and initialise the required system registers and state for the BP to attach and report. Rework the interrupt handler code for this new sequence. Thankfully, this removes a bunch of code for bcm2836mp. The VFP detection handler on <= armv7 relies on the global undefined handler being in place until the BP attaches vfp. That is, after the APs have been spun up. gicv3_its.c has a serialisation issue which is protected against in the gicv3_its_cpu_init, which is called from cpu_hatch, with a spin lock. The serialisation issue needs addressing more completely. Tested on RPI3, Apple M1, QEMU, and lx2k Fixes PR port-arm/56264: diagnostic assertion "l->l_stat == LSONPROC" failed on RPI3
2021-10-31Reload tpidr_el1 into x3 and re-test newipl vs cpl on restart.jmcneill
2021-10-30Add __HAVE_PREEMPTION support to gic_splfuncs asm funcs.jmcneill
"looks right to me" - thorpej
2021-10-30Implement gic_splraise and the gic_splx fast path in asm (armv8).jmcneill
2021-10-21Fix some conditionals to match gicv3 and add some comments to describeskrll
what's going on. Fixes PR port-evbarm/56420
2021-10-02Trailing whitespaceskrll
2021-09-26Add missing insn barrierjmcneill
2021-09-26If an SGI or PPI is established after interrupts are enabled, make surejmcneill
we unblock the source on _all_ CPUs and not just the CPU that is establishing the interrupt.
2021-09-20Make _splraise/_spllower/splx functions available to modules again.jmcneill
2021-09-18gic_splx: performance optimizationsjmcneill
Avoid any kind of register access (DAIF, PMR, etc), barriers, and atomic operations in the common case where no interrupt fires between spl being raised and lowered. This introduces a per-CPU return address (ci_splx_restart) used by the vector handler to restart a sequence in splx that compares the new ipl with the per-CPU hardware priority state stored in ci_hwpl.
2021-09-11GIC: Support SPI affinity routing before secondary CPUs have hatched.jmcneill
Instead of reading MPIDR from CPU init to determine a routing target, trust system configuration data (Devicetree or ACPI) to properly fill in ci_cpuid. This allows for SPI affinity routing to work before secondary CPUs are hatched; previously, one of two things would happen: a) If 1ofN distribution is supported, the SPI could be distributed to any participating PE. b) If 1ofN distribution is not supported, the SPI would not be forwarded and would stay pending.
2021-09-09If we get a spurious interrupt, log a debug message and ignore it.jmcneill
Otherwise we risk tripping an assertion later on due to an interrupt firing before it is scheduled.
2021-08-30- Add an isb before cnt[pv]_ctl readjmcneill
- cntk_ctl is 64-bits - Do not toggle CNTCTL_IMASK in intr handler, as this may be needed elsewhere.
2021-08-10Make gic_splfuncs optional and disable it by default until it has hadjmcneill
more testing.
2021-08-10Use custom spl funcs for GIC and avoid unnecessary pmr register accessesjmcneill
in splx.
2021-08-07Merge thorpej-cfargs2.thorpej
2021-04-24Merge thorpej-cfargs branch:thorpej
Simplify and make extensible the config_search() / config_found() / config_attach() interfaces: rather than having different variants for which arguments you want pass along, just have a single call that takes a variadic list of tag-value arguments. Adjust all call sites: - Simplify wherever possible; don't pass along arguments that aren't actually needed. - Don't be explicit about what interface attribute is attaching if the device only has one. (More simplification.) - Add a config_probe() function to be used in indirect configuiration situations, making is visibly easier to see when indirect config is in play, and allowing for future change in semantics. (As of now, this is just a wrapper around config_match(), but that is an implementation detail.) Remove unnecessary or redundant interface attributes where they're not needed. There are currently 5 "cfargs" defined: - CFARG_SUBMATCH (submatch function for direct config) - CFARG_SEARCH (search function for indirect config) - CFARG_IATTR (interface attribte) - CFARG_LOCATORS (locators array) - CFARG_DEVHANDLE (devhandle_t - wraps OFW, ACPI, etc. handles) ...and a sentinel value CFARG_EOL. Add some extra sanity checking to ensure that interface attributes aren't ambiguous. Use CFARG_DEVHANDLE in MI FDT, OFW, and ACPI code, and macppc and shark ports to associate those device handles with device_t instance. This will trickle trough to more places over time (need back-end for pre-OFW Sun OBP; any others?).
2021-03-28Disable 1ofN distribution of SPIs by default. This is a workaround for anjmcneill
issue in the USB stack -- signaling transfer complete on multiple PEs can cause transfer completions to be processed out of order.
2021-03-28Only target the boot cpu for real with SPI interrupts. I tried to doskrll
this back in 2014, but somehow I missed a spot. This is a quick-and-dirty fix for the USB stack which expects transfer completions to be in-order. If interrupts happen across the CPUs then this isn't guaranteed (yet). kern/55243 panic at usb_transfer_complete() on raspberry pi 4
2021-03-14Remove an unnecessary if statement in gic_v2m_msi_alloc when finding askrll
'count' that fits the available.
2021-02-23If we are committing a deferred splhigh() to hardware, no need to continue.jmcneill
2021-02-21Apply PMR optimizations from gicv3jmcneill
2021-02-21Keep current hardware priority value in struct cpu_info and use it insteadjmcneill
of reading icc_pmr_el1 in gicv3_set_priority.
2021-02-09fix build without MULTIPROCESSORryo
2021-02-09Avoid an extra daif read when dispatching interrupts by usingjakllsch
ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.
2021-02-07Optimize hardware priority updates.jmcneill
In gicv3_set_priority, read the current priority mask and only update it if we are lowering the priority. The hardware priority filter is raised only after taking an interrupt. This makes splfoo/splx without an interrupt in between considerably cheaper as PMR writes are relatively expensive compared to reads. While here, avoid an extra daif read when dispatching interrupts by using ENABLE_INTERRUPT() / DISABLE_INTERRUPT() instead of cpsie() / cpsid() macros.
2021-01-18Fix a commentjmcneill
2021-01-16Remove MAXCPUS dependency.jmcneill
2020-12-24trailing whitespacejmcneill
2020-12-22When lpiconf flushing is required, make sure to flush to PoC and not PoU.jmcneill
Spotted by nick.
2020-12-11Simplify gits_command by getting rid of the _BYTE_ORDER test and justjmcneill
always use the loop + htole64 path.
2020-12-11Preserve ST Lower and Upper fields when clearing Mask bit in the MSI-Xjmcneill
vector control register.
2020-12-11Fix spelling in comment.jmcneill
2020-12-04gicv3: Only use 1 of N SPI distribution when the feature is available.jmcneill
A GICv3+ implementation is not guaranteed to support 1 of N SPI distribution. Support for this feature is indicated in GICD_TYPER.No1N. When No1N=1, route all interrupts to the primary PE by default and only allow a single CPU target when updating affinity.
2020-12-03Provide and use a sev() macro for the sev instruction.skrll
While here use the correct barrier to ensure completion of memory accesses before a couple of the sev() calls.
2020-12-02comparision -> comparisonwiz
2020-11-28Fix buildskrll
2020-11-24Improve detection of NS vs S views of priorities.jmcneill
For PMR, write a 0 to bit7 and see if it sticks. This is only possible from NS EL1 if we have a non-secure view of ICC_PMR_EL1. For int priorities (GICD/GICR interfaces and LPIs), assume that the GICD_CTLR.DS bit is telling us the truth. RK3399 is special here when using the vendor bootloader, so keep the auto-detection from the previous commit but limit the scope to only run on RK3399 SOCs.