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path: root/sys/arch/riscv/include
AgeCommit message (Expand)Author
2023-07-04riscv: Fix (U)INT64_C suffix to match gcc's built-in idea of types.riastradh
2023-06-23Pad the trapframe so it's a multiple of 16 bytes so that when a trapframeskrll
2023-06-12risc-v: MULTIPROCESSOR supportskrll
2023-05-25Fix CLKF_INTR so that not all time is shown as being spent in interrupts.skrll
2023-05-08Don't expose vaddr_t or register_t to userland. The gdb configure scriptskrll
2023-05-08Remove some #if 0'ed codeskrll
2023-05-08KNFskrll
2023-05-07RISC-V support that works on QEMU with a single hart.skrll
2023-04-22G/C pte_indexskrll
2022-12-23Fix RV buildsskrll
2022-12-13KNFskrll
2022-12-03leading whitespace... oopsskrll
2022-12-03Correct some pre-existing relocations and add some new ones.skrll
2022-11-19Fix some typesskrll
2022-11-18Fix SR_WPRI.skrll
2022-11-17Document lots of bits.simonb
2022-11-17Use better types and struct member names in the clockframe.simonb
2022-11-15Use similar macro-magic to aarch64 armreg.h to add per-csrsimonb
2022-11-13Comment fixskrll
2022-11-12Note some SV39 PTE bits defined in extensions.skrll
2022-11-12Use uintptr_t consistently rather than register_tskrll
2022-11-11The supervisor status register is the native word width, not fixedsimonb
2022-11-08Parentheses police.simonb
2022-11-08Add cause register trap types, and some macros to access cause registersimonb
2022-11-08Add a #define for XLEN, the RISC-V native base integer ISA width.simonb
2022-11-08whitepsace nitskrll
2022-10-20Add the "memory" clobber in two places that it's needed.skrll
2022-10-18VSXLEN=64 supports 16-bit ASID space so change tlb_asid_t to be bigskrll
2022-10-18Some fixes from Simon.skrll
2022-10-18Correct XSEGSHIFT for RV32 caseskrll
2022-10-16Map the DTB using VM_KERNEL_DTB_BASE and CONSADDR using VM_KERNEL_IO_BASEskrll
2022-10-15Fix typo in SATP_MODE_SV64skrll
2022-10-15Consistency nit: use "__volatile" instead of "volatile" with asm()s.simonb
2022-10-15Add SATP modes for bare, SV57 and SV64.simonb
2022-10-15Use __volatile so the compiler doesn't optimise out successive callssimonb
2022-10-15#define<tab>simonb
2022-10-15Update a commentskrll
2022-10-12Set RISCV_DIRECTMAP_SIZE to 2^64-PAGESIZE, since 2^64 is effectively 0simonb
2022-10-12Fix a tyop regname in a comment.simonb
2022-10-12NKMEMPAGES_MIN_DEFAULT is in pages not bytes (hint is in the name).simonb
2022-09-30Don't set A, D in page table pointers, but do set them in leaf entries.skrll
2022-09-28Use legacy SBI Console GetChar for earlycons. It works on qemu.skrll
2022-09-27Basic ddb and backtrace support.skrll
2022-09-21Use c99 types. NFC.skrll
2022-09-20Checkpoint WIP.skrll
2022-09-11Add some bus_space(9), bus_dma(9) and FDT infrastructure. Baby steps.skrll
2022-09-10Remove unnecessary cast.skrll
2022-05-24s/dosen't/doesn't/ in copy pasted comment.andvar
2021-10-05#define<tab>jmcneill
2021-10-05Fix riscv32 GENERIC buildskrll