| Age | Commit message (Expand) | Author |
| 2023-02-23 | nvmm: Filter CR4 bits on x86 SVM (AMD). | riastradh |
| 2022-10-06 | Update some AMD CPUID bits: | msaitoh |
| 2022-09-13 | nvmm(4): Add suspend/resume support. | riastradh |
| 2022-08-20 | x86: Split most of pmap.h into pmap_private.h or vmparam.h. | riastradh |
| 2022-08-20 | x86: Move page attribute table bits to x86/pat.h. | riastradh |
| 2022-05-13 | nvmm_x86_vmx.c: remove an #ifdef DIAGNOSTIC, it is wrong since r1.66 | tnn |
| 2021-03-26 | Implement nvmm_vcpu::stop, a race-free exit from nvmm_vcpu_run() without | reinoud |
| 2020-10-24 | Issue 64-bit versions of *XSAVE* for 64-bit amd64 programs | mgorny |
| 2020-09-08 | nvmm-x86: avoid hogging behavior observed recently | maxv |
| 2020-09-08 | nvmm-x86-vmx: improve the handling of CR0 | maxv |
| 2020-09-08 | nvmm: cosmetic changes | maxv |
| 2020-09-06 | Fix fallout from previous uvm.h cleanup. | riastradh |
| 2020-09-05 | Round of uvm.h cleanup. | riastradh |
| 2020-09-05 | x86: fix several CPUID flags | maxv |
| 2020-09-05 | x86: rename PGEX_X -> PGEX_I | maxv |
| 2020-09-05 | nvmm: update copyright headers | maxv |
| 2020-09-04 | nvmm-x86: improve the CPUID emulation | maxv |
| 2020-09-04 | nvmm-x86-vmx: improve the handling of CR0 | maxv |
| 2020-09-04 | nvmm-x86-svm: check the SVM revision | maxv |
| 2020-08-26 | nvmm-x86-svm: improve the handling of MSR_EFER | maxv |
| 2020-08-26 | nvmm-x86: improve the handling of RFLAGS.RF | maxv |
| 2020-08-26 | nvmm-x86-vmx: improve the handling of CR4 | maxv |
| 2020-08-26 | nvmm-x86-svm: don't forget to intercept INVD | maxv |
| 2020-08-22 | nvmm-x86-vmx: fix detection of the BIOS lock | maxv |
| 2020-08-22 | nvmm-x86: hide more CPUID flags, mostly related to perf monitors | maxv |
| 2020-08-22 | nvmm-x86-svm: dedup code | maxv |
| 2020-08-20 | nvmm-x86: improve the CPUID emulation | maxv |
| 2020-08-20 | nvmm-x86: advertise the SERIALIZE instruction, available on future CPUs | maxv |
| 2020-08-18 | nvmm-x86-svm: improve the CPUID emulation | maxv |
| 2020-08-18 | nvmm-x86: also flush the guest TLB when CR4.{PCIDE,SMEP} changes | maxv |
| 2020-08-11 | Micro-optimize: use pushq instead of pushw. To avoid LCP stalls and | maxv |
| 2020-08-11 | Improve the CPUID emulation on nvmm-intel: | maxv |
| 2020-08-11 | Improve emulation of MSR_IA32_ARCH_CAPABILITIES: publish only the *_NO | maxv |
| 2020-08-11 | Hide OSPKE. NFC since the host never uses PKU, but still. | maxv |
| 2020-08-05 | Improve the CPUID emulation: | maxv |
| 2020-08-05 | Add new field definitions, and intercept everything, for future-proofness. | maxv |
| 2020-08-05 | Add new field definitions. | maxv |
| 2020-08-05 | Make it easier to understand what's going on, no functional change. | maxv |
| 2020-08-05 | Use ULL, to make it clear we are unsigned. | maxv |
| 2020-08-05 | Simplify, remove unnecessary #ifdef DIAGNOSTIC around KASSERTs. | maxv |
| 2020-07-19 | Switch to fpu_kern_enter/leave, to prevent clobbering, now that the kernel | maxv |
| 2020-07-19 | The TLB flush IPIs do not respect the IPL, so enforcing IPL_HIGH has no | maxv |
| 2020-07-18 | Now that the IDT is per-CPU, it must be saved/restored on each CPU | maxv |
| 2020-07-14 | Introduce per-cpu IDTs | yamaguchi |
| 2020-07-03 | Print the backend name when attaching. | maxv |
| 2020-06-18 | style | maxv |
| 2020-05-24 | Gather the conditions to return from the VCPU loops in nvmm_return_needed(), | maxv |
| 2020-05-21 | Improve the CPUID emulation on nvmm-intel: limit the highest basic and | maxv |
| 2020-05-10 | Respect the convention for the hypervisor information: return the highest | maxv |
| 2020-05-09 | Improve the CPUID emulation of basic leaves: | maxv |