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2023-02-23nvmm: Filter CR4 bits on x86 SVM (AMD).riastradh
In particular, prohibit PKE, Protection Key Enable, which requires some additional management of CPU state by nvmm.
2022-10-06Update some AMD CPUID bits:msaitoh
- Rename FSREP_MOV to FSRM. - Add Memory Bandwidth Enforcement (MBE) - Add AMD's PPIN. Rename CPUID_SEF_PPIN to CPUID_SEF_INTEL_PPIN. - Add Collaborative Processor Performance Control (CPPC). - Add HOST_MCE_OVERRIDE. - Add some unknown bits as Bxx. - Add comments. - Use __BIT().
2022-09-13nvmm(4): Add suspend/resume support.riastradh
New MD nvmm_impl callbacks: - .suspend_interrupt forces all VMs on all physical CPUs to exit. - .vcpu_suspend suspends an individual vCPU on a machine. - .machine_suspend suspends an individual machine. - .suspend suspends the whole system. - .resume resumes the whole system. - .machine_resume resumes an individual machine. - .vcpu_resume resumes an indidivudal vCPU on a machine. Suspending nvmm: 1. causes new VM operations (ioctl and close) to block until resumed, 2. uses .suspend_interrupt to interrupt any concurrent and force them to return early, and then 3. uses the various suspend callbacks to suspend all vCPUs, machines, and the whole system -- all vCPUs before the machine they're on, and all machines before the system. Resuming nvmm does the reverse of (3) -- resume system, resume each machine and then the vCPUs on that machine -- and then unblocks operations. Implemented only for x86-vmx for now: - suspend_interrupt triggers a TLB IPI to cause VM exits; - vcpu_suspend issues VMCLEAR to force any in-CPU state to be written to memory; - machine_suspend does nothing; - suspend does VMXOFF on all CPUs; - resume does VMXON on all CPUs; - machine_resume does nothing; and - vcpu_resume just marks each vCPU as valid but inactive so subsequent use will clear it and load it with vmptrld. x86-svm left as an exercise for the reader.
2022-08-20x86: Split most of pmap.h into pmap_private.h or vmparam.h.riastradh
This way pmap.h only contains the MD definition of the MI pmap(9) API, which loads of things in the kernel rely on, so changing x86 pmap internals no longer requires recompiling the entire kernel every time. Callers needing these internals must now use machine/pmap_private.h. Note: This is not x86/pmap_private.h because it contains three parts: 1. CPU-specific (different for i386/amd64) definitions used by... 2. common definitions, including Xenisms like xpmap_ptetomach, further used by... 3. more CPU-specific inlines for pmap_pte_* operations So {amd64,i386}/pmap_private.h defines 1, includes x86/pmap_private.h for 2, and then defines 3. Maybe we should split that out into a new pmap_pte.h to reduce this trouble. No functional change intended, other than that some .c files must include machine/pmap_private.h when previously uvm/uvm_pmap.h polluted the namespace with pmap internals. Note: This migrates part of i386/pmap.h into i386/vmparam.h -- specifically the parts that are needed for several constants defined in vmparam.h: VM_MAXUSER_ADDRESS VM_MAX_ADDRESS VM_MAX_KERNEL_ADDRESS VM_MIN_KERNEL_ADDRESS Since i386 needs PDP_SIZE in vmparam.h, I added it there on amd64 too, just to keep things parallel.
2022-08-20x86: Move page attribute table bits to x86/pat.h.riastradh
2022-05-13nvmm_x86_vmx.c: remove an #ifdef DIAGNOSTIC, it is wrong since r1.66tnn
2021-03-26Implement nvmm_vcpu::stop, a race-free exit from nvmm_vcpu_run() withoutreinoud
signals. This introduces a new kernel and userland NVMM version indicating this support. Patch by Kamil Rytarowski <kamil@netbsd.org> and committed on his request.
2020-10-24Issue 64-bit versions of *XSAVE* for 64-bit amd64 programsmgorny
When calling FXSAVE, XSAVE, FXRSTOR, ... for 64-bit programs on amd64 use the 64-suffixed variant in order to include the complete FIP/FDP registers in the x87 area. The difference between the two variants is that the FXSAVE64 (new) variant represents FIP/FDP as 64-bit fields (union fp_addr.fa_64), while the legacy FXSAVE variant uses split fields: 32-bit offset, 16-bit segment and 16-bit reserved field (union fp_addr.fa_32). The latter implies that the actual addresses are truncated to 32 bits which is insufficient in modern programs. The change is applied only to 64-bit programs on amd64. Plain i386 and compat32 continue using plain FXSAVE. Similarly, NVMM is not changed as I am not familiar with that code. This is a potentially breaking change. However, I don't think it likely to actually break anything because the data provided by the old variant were not meaningful (because of the truncated pointer).
2020-09-08nvmm-x86: avoid hogging behavior observed recentlymaxv
When the FPU code got rewritten in NetBSD, the dependency on IPL_HIGH was eliminated, and I took _vcpu_guest_fpu_enter() out of the VCPU loop since there was no need to be in the splhigh window. Later, the code was switched to use the kernel FPU API, API that works at IPL_VM, not at IPL_NONE. These two changes mean that the whole VCPU loop is now executing at IPL_VM, which is not desired, because it introduces a delay in interrupt processing on the host in certain cases. Fix this by putting _vcpu_guest_fpu_enter() back inside the VCPU loop.
2020-09-08nvmm-x86-vmx: improve the handling of CR0maxv
- CR0_ET is hard-wired to 1 in the cpu, so force CR0_ET to 1 in the shadow. - Clarify.
2020-09-08nvmm: cosmetic changesmaxv
- Style. - Explicitly include ioccom.h.
2020-09-06Fix fallout from previous uvm.h cleanup.riastradh
- pmap(9) needs uvm/uvm_extern.h. - x86/pmap.h is not usable on its own; it is only usable if included via uvm/uvm_extern.h (-> uvm/uvm_pmap.h -> machine/pmap.h). - Make nvmm.h and nvmm_internal.h standalone.
2020-09-05Round of uvm.h cleanup.riastradh
The poorly named uvm.h is generally supposed to be for uvm-internal users only. - Narrow it to files that actually need it -- mostly files that need to query whether curlwp is the pagedaemon, which should maybe be exposed by an external header. - Use uvm_extern.h where feasible and uvm_*.h for things not exposed by it. We should split up uvm_extern.h but this will serve for now to reduce the uvm.h dependencies. - Use uvm_stat.h and #ifdef UVMHIST uvm.h for files that use UVMHIST(ubchist), since ubchist is declared in uvm.h but the reference evaporates if UVMHIST is not defined, so we reduce header file dependencies. - Make uvm_device.h and uvm_swap.h independently includable while here. ok chs@
2020-09-05x86: fix several CPUID flagsmaxv
- Rename: CPUID_PN -> CPUID_PSN CPUID_CFLUSH -> CPUID_CLFSH CPUID_SBF -> CPUID_PBE CPUID_LZCNT -> CPUID_ABM CPUID_P1GB -> CPUID_PAGE1GB CPUID2_PCLMUL -> CPUID2_PCLMULQDQ CPUID2_CID -> CPUID2_CNXTID CPUID2_xTPR -> CPUID2_XTPR CPUID2_AES -> CPUID2_AESNI To match the x86 specification and the other OSes. - Remove: CPUID_B10, CPUID_B20, CPUID_IA64. They do not exist.
2020-09-05x86: rename PGEX_X -> PGEX_Imaxv
To match the x86 specification and the other OSes.
2020-09-05nvmm: update copyright headersmaxv
2020-09-04nvmm-x86: improve the CPUID emulationmaxv
- Mask DTES64, DS_CPL, CID, SDBG, xTPR, PN. - B10, B20 and IA64 do not exist, so just remove them.
2020-09-04nvmm-x86-vmx: improve the handling of CR0maxv
- Flush the guest TLB when certain CR0 bits change. - If the guest updates a static bit in CR0, then reflect the change in VMCS_CR0_SHADOW, for the guest to get the illusion that the change was applied. The "real" CR0 static bits remain unchanged. - In vmx_vcpu_{g,s}et_state(), take VMCS_CR0_SHADOW into account. - Slightly modify the CR4 handling code, just for more symmetry with CR0.
2020-09-04nvmm-x86-svm: check the SVM revisionmaxv
Only revision 1 exists, but check it, for future-proofness.
2020-08-26nvmm-x86-svm: improve the handling of MSR_EFERmaxv
Intercept reads of it as well, just to mask EFER_SVME, which the guest doesn't need to see.
2020-08-26nvmm-x86: improve the handling of RFLAGS.RFmaxv
- When injecting certain exceptions, set RF. For us to have an up-to-date view of RFLAGS, we commit the state before the event. - When advancing RIP, clear RF.
2020-08-26nvmm-x86-vmx: improve the handling of CR4maxv
- Filter out certain features we don't want the guest to enable. This is for general correctness, and future-proofness. - Flush the guest TLB when certain flags change.
2020-08-26nvmm-x86-svm: don't forget to intercept INVDmaxv
INVD executed in the guest can be dangerous for the host, due to CPU caches being flushed without write-back.
2020-08-22nvmm-x86-vmx: fix detection of the BIOS lockmaxv
If it's locked, ensure it's locked with VMX enabled. If it's not locked, then lock it ourselves with VMX enabled. Should fix NetBSD PR/55596.
2020-08-22nvmm-x86: hide more CPUID flags, mostly related to perf monitorsmaxv
2020-08-22nvmm-x86-svm: dedup codemaxv
2020-08-20nvmm-x86: improve the CPUID emulationmaxv
- x86-svm: explicitly handle 0x80000007 and 0x80000008. The latter contains extended features we must filter out. Apply the same in x86-vmx for symmetry. - x86-svm: explicitly handle extended leaves until 0x8000001F, and truncate to it.
2020-08-20nvmm-x86: advertise the SERIALIZE instruction, available on future CPUsmaxv
2020-08-18nvmm-x86-svm: improve the CPUID emulationmaxv
Limit the hypervisor range, and properly handle each basic leaf until 0xD.
2020-08-18nvmm-x86: also flush the guest TLB when CR4.{PCIDE,SMEP} changesmaxv
2020-08-11Micro-optimize: use pushq instead of pushw. To avoid LCP stalls andmaxv
unaligned stack accesses.
2020-08-11Improve the CPUID emulation on nvmm-intel:maxv
- Limit the highest extended leaf. - Limit 0x00000007 to ECX=0, for future-proofness.
2020-08-11Improve emulation of MSR_IA32_ARCH_CAPABILITIES: publish only the *_NOmaxv
bits. Initially they were the only ones there, but Intel then added other bits we aren't interested in, and they must be filtered out.
2020-08-11Hide OSPKE. NFC since the host never uses PKU, but still.maxv
2020-08-05Improve the CPUID emulation:maxv
- Hide SGX*, PKU, WAITPKG, and SKINIT, because they are not supported. - Hide HLE and RTM, part of TSX. Because TSX is just too buggy and we cannot guarantee that it remains enabled in the guest (if for example the host disables TSX while the guest is running). Nobody wants this crap anyway, so bye-bye. - Advertise FSREP_MOV, because no reason to hide it.
2020-08-05Add new field definitions, and intercept everything, for future-proofness.maxv
2020-08-05Add new field definitions.maxv
2020-08-05Make it easier to understand what's going on, no functional change.maxv
2020-08-05Use ULL, to make it clear we are unsigned.maxv
2020-08-05Simplify, remove unnecessary #ifdef DIAGNOSTIC around KASSERTs.maxv
2020-07-19Switch to fpu_kern_enter/leave, to prevent clobbering, now that the kernelmaxv
itself uses the fpu.
2020-07-19The TLB flush IPIs do not respect the IPL, so enforcing IPL_HIGH has nomaxv
effect. Disable interrupts earlier instead. This prevents a possible race against such IPIs.
2020-07-18Now that the IDT is per-CPU, it must be saved/restored on each CPUmaxv
independently.
2020-07-14Introduce per-cpu IDTsyamaguchi
This is realized by following modifications: - Add IDT pages and its allocation maps for each cpu in "struct cpu_info" - Load per-cpu IDTs at cpu_init_idt(struct cpu_info*) - Copy the IDT entries for cpu0 to other CPUs at attach - These are, for example, exceptions, db, system calls, etc. And, added a kernel option named PCPU_IDT to enable the feature.
2020-07-03Print the backend name when attaching.maxv
2020-06-18stylemaxv
2020-05-24Gather the conditions to return from the VCPU loops in nvmm_return_needed(),maxv
and use it in nvmm_do_vcpu_run() as well. This fixes two undesired behaviors: - When a VM initializes, the many nested page faults that need processing could cause the calling thread to occupy the CPU too much if we're unlucky and are only getting repeated nested page faults thousands of times in a row. - When the emulator calls nvmm_vcpu_run() and immediately sends a signal to stop the VCPU, it's better to check signals earlier and leave right away, rather than doing a round of VCPU run that could increase the time spent by the emulator waiting for the return.
2020-05-21Improve the CPUID emulation on nvmm-intel: limit the highest basic andmaxv
hypervisor leaves.
2020-05-10Respect the convention for the hypervisor information: return the highestmaxv
hypervisor leaf in 0x40000000.EAX.
2020-05-09Improve the CPUID emulation of basic leaves:maxv
- Hide DCA and PQM, they cannot be used in guests. - On Intel, explicitly handle each basic leaf until 0x16. - On AMD, explicitly handle each basic leaf until 0x0D.