| Age | Commit message (Expand) | Author |
| 2019-04-27 | Optimize nvmm-intel, use inlined GCC assembly rather than function calls. | maxv |
| 2019-04-24 | Match the structure order, for better cache utilization. | maxv |
| 2019-04-24 | Provide the hardware error code for NVMM_EXIT_INVALID, useful when | maxv |
| 2019-04-20 | Ah, take XSAVE into account in ECX too, not just in EBX. Otherwise if the | maxv |
| 2019-04-10 | Add the NVMM_CTL ioctl, always privileged regardless of the permissions of | maxv |
| 2019-04-08 | Switch to MODULE_CLASS_MISC, from pgoyette@. | maxv |
| 2019-04-08 | Don't forget to call (*machine_destroy) when killing VMs. | maxv |
| 2019-04-08 | Use the fd_clone approach, to avoid losing references to the registered | maxv |
| 2019-04-07 | Invert the filtering priority: now the kernel-managed cpuid leaves are | maxv |
| 2019-04-07 | Don't allow unloading when there are still VMs registered, and don't allow | maxv |
| 2019-04-06 | Replace the misc[] state by a new compressed nvmm_x64_state_intr structure, | maxv |
| 2019-04-03 | VMX: if PAT is not valid, #GP on WRMSR, rather than crashing the guest. | maxv |
| 2019-04-03 | Add new VMCS bits. | maxv |
| 2019-04-03 | Add MSR_TSC. | maxv |
| 2019-03-28 | Move NVMM in the "any" class, so that it can be enabled in GENERIC. Add | maxv |
| 2019-03-21 | Make it possible for an emulator to set the protection of the guest pages. | maxv |
| 2019-03-14 | Optimize NVMM-Intel: keep the VMCS active on the host CPU, and lazy-switch | maxv |
| 2019-03-14 | Move a KASSERT, applies to all branches. | maxv |
| 2019-03-14 | Reduce the mask of the VTPR, only the first four bits matter. | maxv |
| 2019-03-14 | Fail early if we're beyond the guest max ram. | maxv |
| 2019-03-07 | Rename the internal NVMM HVA table entries from "segment" to "hmapping", | maxv |
| 2019-03-07 | Parse EXC_NMI on nvmm-intel, and don't return NVMM_EXIT_INVALID if we | maxv |
| 2019-03-03 | Choose which CPUID bits to allow, rather than which bits to disallow. This | maxv |
| 2019-02-26 | Change the layout of the SEG state: | maxv |
| 2019-02-23 | Install the x86 RESET state at VCPU creation time, for convenience, so | maxv |
| 2019-02-23 | Add support for CPUs that don't have the EPT_{A,D} bits. | maxv |
| 2019-02-23 | Reorder the functions, and constify setstate. No functional change. | maxv |
| 2019-02-22 | Fix omission: if we receive a guest trap on CR0, and if the original | maxv |
| 2019-02-21 | Reorder the detection in vmx_ident(), to fix panic on old CPUs. We must | maxv |
| 2019-02-21 | Another locking issue in NVMM: the {svm,vmx}_tlb_flush functions take VCPU | maxv |
| 2019-02-21 | Clarify the gTLB code a little. | maxv |
| 2019-02-18 | Ah, finally found you. Fix scheduling bug in NVMM. | maxv |
| 2019-02-16 | Ah no, adapt previous, on AMD RAX is in the VMCB. | maxv |
| 2019-02-16 | Improve the FPU detection: hide XSAVES because we're not allowing it, and | maxv |
| 2019-02-16 | Handle MSR_MISC_ENABLE on NVMM-Intel (Intel-specific). | maxv |
| 2019-02-15 | Initialize the guest TSC to zero at VCPU creation time, and handle guest | maxv |
| 2019-02-14 | Harmonize the handling of the CPL between AMD and Intel. | maxv |
| 2019-02-14 | On AMD, the segments have a simple "present" bit. On Intel however there | maxv |
| 2019-02-13 | Add Intel-VMX support in NVMM. This allows us to run hardware-accelerated | maxv |
| 2019-02-13 | Drop support for software interrupts. I had initially added that to cover | maxv |
| 2019-02-13 | Micro optimization: the STAR/LSTAR/CSTAR/SFMASK MSRs are static, so rather | maxv |
| 2019-02-13 | Reorder the GPRs to match the CPU encoding, simplifies things on Intel. | maxv |
| 2019-02-12 | Optimize: the hardware does not clear the TLB flush command after a | maxv |
| 2019-02-11 | Increase the max guest ram from 4GB to 128GB. | maxv |
| 2019-02-04 | Improvements: | maxv |
| 2019-01-26 | Optimize: keep a per-VCPU buffer for the state, and copy in and out | maxv |
| 2019-01-26 | Remove nvmm_exit_memory.npc, useless. | maxv |
| 2019-01-24 | Optimize: change the behavior of the HLT vmexit, make it a "change in vcpu | maxv |
| 2019-01-20 | Improvements in NVMM | maxv |
| 2019-01-13 | Reset DR7 before loading DR0-3, to prevent a fault if the host process | maxv |