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path: root/sys/dev/nvmm
AgeCommit message (Expand)Author
2019-04-27Optimize nvmm-intel, use inlined GCC assembly rather than function calls.maxv
2019-04-24Match the structure order, for better cache utilization.maxv
2019-04-24Provide the hardware error code for NVMM_EXIT_INVALID, useful whenmaxv
2019-04-20Ah, take XSAVE into account in ECX too, not just in EBX. Otherwise if themaxv
2019-04-10Add the NVMM_CTL ioctl, always privileged regardless of the permissions ofmaxv
2019-04-08Switch to MODULE_CLASS_MISC, from pgoyette@.maxv
2019-04-08Don't forget to call (*machine_destroy) when killing VMs.maxv
2019-04-08Use the fd_clone approach, to avoid losing references to the registeredmaxv
2019-04-07Invert the filtering priority: now the kernel-managed cpuid leaves aremaxv
2019-04-07Don't allow unloading when there are still VMs registered, and don't allowmaxv
2019-04-06Replace the misc[] state by a new compressed nvmm_x64_state_intr structure,maxv
2019-04-03VMX: if PAT is not valid, #GP on WRMSR, rather than crashing the guest.maxv
2019-04-03Add new VMCS bits.maxv
2019-04-03Add MSR_TSC.maxv
2019-03-28Move NVMM in the "any" class, so that it can be enabled in GENERIC. Addmaxv
2019-03-21Make it possible for an emulator to set the protection of the guest pages.maxv
2019-03-14Optimize NVMM-Intel: keep the VMCS active on the host CPU, and lazy-switchmaxv
2019-03-14Move a KASSERT, applies to all branches.maxv
2019-03-14Reduce the mask of the VTPR, only the first four bits matter.maxv
2019-03-14Fail early if we're beyond the guest max ram.maxv
2019-03-07Rename the internal NVMM HVA table entries from "segment" to "hmapping",maxv
2019-03-07Parse EXC_NMI on nvmm-intel, and don't return NVMM_EXIT_INVALID if wemaxv
2019-03-03Choose which CPUID bits to allow, rather than which bits to disallow. Thismaxv
2019-02-26Change the layout of the SEG state:maxv
2019-02-23Install the x86 RESET state at VCPU creation time, for convenience, somaxv
2019-02-23Add support for CPUs that don't have the EPT_{A,D} bits.maxv
2019-02-23Reorder the functions, and constify setstate. No functional change.maxv
2019-02-22Fix omission: if we receive a guest trap on CR0, and if the originalmaxv
2019-02-21Reorder the detection in vmx_ident(), to fix panic on old CPUs. We mustmaxv
2019-02-21Another locking issue in NVMM: the {svm,vmx}_tlb_flush functions take VCPUmaxv
2019-02-21Clarify the gTLB code a little.maxv
2019-02-18Ah, finally found you. Fix scheduling bug in NVMM.maxv
2019-02-16Ah no, adapt previous, on AMD RAX is in the VMCB.maxv
2019-02-16Improve the FPU detection: hide XSAVES because we're not allowing it, andmaxv
2019-02-16Handle MSR_MISC_ENABLE on NVMM-Intel (Intel-specific).maxv
2019-02-15Initialize the guest TSC to zero at VCPU creation time, and handle guestmaxv
2019-02-14Harmonize the handling of the CPL between AMD and Intel.maxv
2019-02-14On AMD, the segments have a simple "present" bit. On Intel however theremaxv
2019-02-13Add Intel-VMX support in NVMM. This allows us to run hardware-acceleratedmaxv
2019-02-13Drop support for software interrupts. I had initially added that to covermaxv
2019-02-13Micro optimization: the STAR/LSTAR/CSTAR/SFMASK MSRs are static, so rathermaxv
2019-02-13Reorder the GPRs to match the CPU encoding, simplifies things on Intel.maxv
2019-02-12Optimize: the hardware does not clear the TLB flush command after amaxv
2019-02-11Increase the max guest ram from 4GB to 128GB.maxv
2019-02-04Improvements:maxv
2019-01-26Optimize: keep a per-VCPU buffer for the state, and copy in and outmaxv
2019-01-26Remove nvmm_exit_memory.npc, useless.maxv
2019-01-24Optimize: change the behavior of the HLT vmexit, make it a "change in vcpumaxv
2019-01-20Improvements in NVMMmaxv
2019-01-13Reset DR7 before loading DR0-3, to prevent a fault if the host processmaxv